TDA4AL-Q1: [PSDK RTOS 10.01] Raise MCU R5F DDR access priority via CBASS QoS in SBL/SPL (request minimal patch)

Hi Sanhsin Kuo,

Could you please share high level dataflow and DDR BW that this dataflow is using? This will help us to debug it further.

Regards,

Brijesh 

Hi Brijesh Jadav   

      We are suffering  an issue similar to the one described in   TDA4VL-Q1: MCU DDR access priority .

The problem is related to the MCU R5F DDR access priority, but we are using a different PDK version, pdk_j721s2_10_01_00_25. The patch provided for the TDA4VL-Q1 issue is incompatible with our version.

Could you the patch to Raise MCU R5F DDR access priority  based on pdk_j721s2_10_01_00_25?

The High level data flow is like the below diagram.

Thanks a lot.

SanHsin

CC: Lance Shen , Gibbs Shih 

Hi SanHsin,

but can you copy the same API ie setup_mcu_r5f_qos in the SBL, rebuild SBL and see if it helps? 

Regards,

Brijesh

HI Brijesh Jadav :

    >>but can you copy the same API ie setup_mcu_r5f_qos in the SBL, rebuild SBL and see if it helps? 

Could you please provide specific guidance on how to configure the QoS to raise the DDR access priority for the MCU R5F?

We are not clear on the required steps and would appreciate your help

Thanks

SanHsin

Hi SanHsin,

My suggestion here is to refer to TRM for QoS parameters understanding. 

Regards,

Brijesh 

Hi Gibbs Shih , Brijesh Jadav  CC: Lance Shen 

   We need your techical support, experience to speed up our CRITICAL MCU Loading issue.

According to the patches  raise the DDR access priority for the MCU R5F from TDA4VL-Q1: MCU DDR access priority,

   these below patches cannot  be applied into pdk_j721s2_10_01_00_25.,  also cannot find the API setup_mcu_r5f_qos Brijesh Jadav  mentioned from below patches , u-boot , pdk source files.

0001-Added-QOS-support-for-DSS-on-J721S2.patch
5305.0001-Added-QoS-parameters-settings.patch
QoS_For_mcu3_mcu1.patch.

There is no he API setup_mcu_r5f_qos Brijesh Jadav  mentioned from the patch 0001-Added-QOS-support-for-DSS-on-J721S2.patch 
285: +void setup_navss_nb(void)
292: +void setup_vpac_qos(void)
321: +void setup_dmpac_qos(void)
332: +void setup_dss_qos(void)
365: +void setup_gpu_qos(void)
432: +void setup_encoder_qos(void)
461: +void setup_decoder_qos(void)

Could you please help us where to find  the API setup_mcu_r5f_qos in the SBL?  or  provide the patch to Raise MCU R5F DDR access priority  based on pdk_j721s2_10_01_00?

Thanks a lot.

SanHsin

Hi, Brijesh

Thanks you replies 

I try to study this patch.

/cfs-file/__key/communityserver-discussions-components-files/791/0001_2D00_Added_2D00_QOS_2D00_support_2D00_for_2D00_DSS_2D00_on_2D00_J721S2.patch

+#define QOS_R5FSS0_CORE0_MEM_RD                     0x45d84000
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH            3
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH            1
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j)   (QOS_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j)   (QOS_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i)        (QOS_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)

for example,

May I know where is the register name (address) for QOS_R5FSS0_CORE0_MEM_RD in TRM?

Because I try to re-map this define between patch code & TRM (spruj28f), but I don not find right context

we try to modify this patch for QOS_MCUSS_R5.

Thank You.

Gibbs

Hi Gibbs,

These registers are available at the offset 0x45D84000, as per below macros. It should remain same even of J721S2. 

+#define QOS_R5FSS0_CORE0_MEM_RD 0x45d84000
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH 3
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH 1
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j) (QOS_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j) (QOS_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i) (QOS_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)

Regards,

Brijesh

Also for MCU R5F, they are available at 

#define QOS_MCU_R5FSS0_CORE0_MEM_RD 0x45d10000
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_J_CH 1
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_I_CH 1
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)

Regards,

Brijesh

Hello, Brijesh

Thanks you replies.

I think patch code should be like as below, Could you help me double check it for "red mark ones"?

Thank You Very Much

Gibbs

#define QOS_MCU_R5FSS0_CORE0_MEM_RD 0x45d10000
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_J_CH 1
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_I_CH 1
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)

#define QOS_MCU_R5FSS0_CORE1_MEM_RD 0x45d11000
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_NUM_J_CH 1
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_NUM_I_CH 1
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(j) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(j) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_MAP(i) (QOS_MCU_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)

#define QOS_MCU_R5FSS0_CORE0_MEM_WR 0x45d10400
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_J_CH 1
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_I_CH 1
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(j) (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(j) (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_MAP(i) (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x100 + (i) * 4)

#define QOS_MCU_R5FSS0_CORE1_MEM_WR 0x45d11400
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_NUM_J_CH 1
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_NUM_I_CH 1
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(j) (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x0 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(j) (QOS_MCU_R5FSS0_CORE0_MEM_WR + 0x4 + (j) * 8)
#define QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_MAP(i) (QOS_MCU_R5FSS0_CORE1_MEM_WR + 0x100 + (i) * 4)

+#define QOS_MCU_R5FSS0_CORE0_MEM_RD_ATYPE (0U)
+#define QOS_MCU_R5FSS0_CORE0_MEM_WR_ATYPE (0U)
+#define QOS_MCU_R5FSS0_CORE1_MEM_RD_ATYPE (0U)
+#define QOS_MCU_R5FSS0_CORE1_MEM_WR_ATYPE (0U)

void setup_mcu_r5f_qos(void)
{
unsigned int channel, group;

/* R5FSS0 core0 - read */
for (group = 0; group < QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
}

for (channel = 0; channel < QOS_MCU_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
}

/* R5FSS0 core0 - write */
for (group = 0; group < QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
}

for (channel = 0; channel < QOS_MCU_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
}

/* R5FSS0 core1 - read */
for (group = 0; group < QOS_MCU_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
}

for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
}

/* R5FSS0 core1 - write */
for (group = 0; group < QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH; ++group)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
}

for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel)
{
CSL_REG32_WR((uintptr_t)QOS_MCU_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel), (QOS_MCU_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_MCU_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_MCU_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4));
}
}

Hi Gibbs,

Looking at the register specs, it looks to be correct. 

Regarding AType value, it is configurable, so it is upto customer to select appropriate value for their usecase. 

Regards,

Brijesh 

Hi, Brijesh

I try to find definition what's AType value mean.

I think AType value should be 0~3.( 0 = physical. 1 = intermediate. 2 = virtual. 3 = physical with coherence. )

Could you tell us what's the different for each one?

Thank You.

Gibbs