PROCESSOR-SDK-J784S4: Validation of SerDes2 Lane0 DTS Configuration for SGMII5 → DP83869 → ADIN1100

Tool/software:

Hi,

I have the following Ethernet setup on J784S4:

CPSW9G (port5) <--> SGMII <--> DP83869 (addr 3) <--> RGMII <--> ADIN1100 (addr 0)

The DP83869 SGMII-to-RGMII PHY is connected over `SGMII5` via `SERDES2_LANE0`. On the SoC side, `SGMII5_RX0_P/N` and `TX0_P/N` are routed to `SERDES2_RX0_P/N` and `TX0_P/N` respectively.

My current DTS configuration for SerDes2 lane0 is:

&serdes_refclk {
    clock-frequency = <100000000>;
};

&serdes_ln_ctrl {
    idle-states = <J784S4_SERDES2_LANE0_QSGMII_LANE5>;
};

&serdes_wiz2 {
    status = "okay";
};

&serdes2 {
    status = "okay";
    #address-cells = <1>;
    #size-cells = <0>;
    serdes2_sgmii_link: phy@0 {
        reg = <0>;
        cdns,num-lanes = <1>;
        #phy-cells = <0>;
        cdns,phy-type = <PHY_TYPE_SGMII>;
        resets = <&serdes_wiz2 1>;
    };
};

&main_cpsw0 {
  status = "okay";
};

&main_cpsw0_mdio {
  status = "okay";
  pinctrl-names = "default";
  pinctrl-0 = <&main_cpsw9x1_mdio_pins_default>;
  pinctrl-1 = <&_main_pmx_gpio_vddshv20_pins_default>;

  /* DP83869 Bridge PHY - Connected to CPSW SGMII port */
  bridge_phy: ethernet-phy@3 {
    reg = <3>;// DP83869 address
    };
  };

  /* ADIN1100 - Connected via RGMII to DP83869 bridge */
  adin1100: ethernet-phy@0 {
    reg = <0>;  // ADIN1100 behind DP83869

  };

};

&main_cpsw0_port5 {
  status = "okay";
  phy-mode = "sgmii";
  phy-handle = <&adin1100>;
  phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_sgmii_link>;
  phy-names = "mac", "serdes";

};

I want to confirm:

1. Are all the SerDes2 lane0-related entries correct for connecting SGMII5 to the DP83869?
2. How can I validate in DTS or at runtime that SerDes2 is configured properly and working?

Thanks in advance.

Dharanija