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AM5706: AM5706 PCIE Schematic Check

Vladislav Shmelev
Prodigy 30 points
Part Number: AM5706

Tool/software:

Hello TI Team,

Could you please review the PCIe reference clock connection for the AM5706?

My design uses the LJCB_CLK in Output REFCLK mode. The ljcb_clkn / ljcb_clkp pins are intended to provide a HCSL reference clock to the link partner (an Artix-7 FPGA).

Please advise if this is correct.

Thank you for your help.


AM5706+ARTIX7_PCIE.pdf

  • +1
    TI__Guru 52465 points

    The LJCB_CLK pins generate a HCSL compliant reference clock. If the receiver expects an HCSL compliant clock source, then only the 50-ohm to GND resistors are needed. These should not be AC-coupled as shown in your schematic (no in-line capacitors).  You could replace the capacitors with 0-ohm resistors it give flexibility when testing your clock setup.

  • 0 in reply to Robert Eschler
    Prodigy 30 points

    Hello Robert,

    Thank you for your advice. The receiver expects an LVDS signal and has an internal bias with 100-Ohm termination, so I will need AC coupling capacitors.

    Could you also confirm my understanding regarding the clock stability for PCIe? If I understand correctly, the LJCB_CLK gets its clock from an internal PLL, which is sourced from SYS_CLK1. I have selected a 20 MHz, 10 ppm oscillator. Is this sufficient for PCIe requirements?

    Thank you.

  • 0 in reply to Vladislav Shmelev
    TI__Guru 52465 points

    Yes sufficient for PCIe clocking requirements.