DRA829V: Intermittent hang when handing over to U-Boot proper

Hi Bo,

The TI resource assigned to this post, is currently out of office, please be aware that there will be a delay in response.

Regards,

kb

Hi Bo,

This is seen at the A72 SPL boot stage. At this point the DDR is up and running.

U-boot is being loaded from the qspi to DDR.

Can you check if A72 is executing u-boot or hangs are SPL level trying to load the u-boot image?

Best Regards,

Keerthy 

Hi Keerthy,

I have reproduced this on the EVM platform as we first saw it on out custom device.

This is a log from my own device when it hangs:

U-Boot SPL 2024.04-ti-gda00c65d74dc (Oct 02 2025 - 08:57:18 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
>>> boot_from_devices
Trying to boot from SPI
cadence_spi spi@47050000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47050000 ahbbase=58000000 max-frequency=40000000 page-size=256
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
Authentication passed
Authentication passed
Authentication passed
>>> spl_perform_fixups
>>> bootstage_mark_name
>>> spl_board_prepare_for_boot
>>> HANDOVER to A72
Loading Environment from nowhere... OK
Authentication passed
Authentication passed
Starting ATF on ARM64 core...

NOTICE:  BL31: v2.11.0(release):v2.11.0-906-g58b25570c9-dirty
NOTICE:  BL31: Built : 08:49:40, Aug  5 2025
I/TC:
I/TC: OP-TEE version: 4.4.0-dev (gcc version 13.3.0 (GCC)) #1 Tue Jul  1 15:17:54 UTC 2025 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: HUK Initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04-ti-gda00c65d74dc (Oct 02 2025 - 08:57:19 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
Successfully set the A72 clock frequency to 1000000000
Successfully set the MSMC clock frequency to 500000000
>>> boot_from_devices
Trying to boot from SPI
cadence_spi spi@47050000: Unable to find PHY pattern partition
Authentication passed
Authentication passed
>>> spl_perform_fixups
>>> bootstage_mark_name
>>> spl_board_prepare_for_boot
>>> HANDOVER to A72
image entry point: 0x80800000


(hangs here)

The last debug printout is from this function, in spl.c:

__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
	typedef void __noreturn (*image_entry_noargs_t)(void);

	image_entry_noargs_t image_entry =
		(image_entry_noargs_t)spl_image->entry_point;

	debug("image entry point: 0x%lx\n", spl_image->entry_point);
	image_entry();
}

This is as far as I have been able to trace it. But please read up on the previous e2e, linked in my first post. They have observed an issue with MCU_RESETSTATz and RESETSTATz being held low when this error occurs.

This has now been observed on two different platforms (AM69 and DRA829), which makes me think that this is a fundamental flaw in the k3 architecture boot process.

A colleague of mine has experimented with swapping out tiboot3.bin and sysfw.itb to older versions based on U-Boot 2023.04 and SYSFW ABI version 10.0.1, which has shows a better stability (say 1 in 10000 boots) but they still hang in the handover if let run long enough.

Also note that our device, based on DRA829V, now has been released and is an active product on the market. I can not stress enough that this problem keeps us awake at night, so please escalate it to the highest instance.

Regards,

/Bo