Tool/software:
Hi Support Team,
Please allow me to confirm a similar case regarding the following thread:
e2e.ti.com/.../am6442-ddr-tck-margin-and-speed-change
The results of the DDR compliance test for the AM6442 was “Fail”
for the “tCK(avg) Rising Edge Measurements (JEDEC Standard No. 79-4D, Table 172)”.
Specification: 1.25 ns ≤ tCK(avg) ≤ 1.50 ns
Results:
Minimum: 1.249710 ns
Average: 1.249996 ns
Maximum: 1.250302 ns
The testing agency's opinion was: “The specification lower limit is 1.250 ns,
which is the clock period at 1600 Mbps. Since this is an evaluation item prone to failure,
operation is considered acceptable.” However, the end user inquired as follows:
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Q1. Regarding the clock specification, why is it set that way?
Q2. If it's 800 MHz, the median should be 1.25 ns. Where does this specification come from?
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The referenced thread above contains the following comment.
Paul said;
The PLL that sources this clock has variations that were accounted for during timing closure of the device.
Therefore, you do not need to reduce the frequency to account for the datasheet minimum clock period.
Could you please provide documentation clearly stating that the PLL supplying this clock has variations
that were accounted for during the device's timing closure and that this is not an issue?
Best Regards,
Kanae