AM625: Boot mode buffers

prema R

Part Number: AM625
Other Parts Discussed in Thread: , , AM623, AM620-Q1, AM62D-Q1

We are using AM6254 in our HMI design. We are using the boot mode pins for multifunction. Few pins are used as boot mode and also used to connect to HDMI transmitter. Hence we have used isolation resistors and buffers for all the boot mode pins. Please clarify

- whether buffers are required or isolation resisors sufficient
- pull up,pull down values for boot mode are ok ?
- supply for the buffers VCCA and VCCB of buffers can be from the same source
Below are snapshots of the schematics.

3 months ago

0 Kallikuppa Sreenivasa 3 months ago

TI__Guru**** 211260 points

Hello prema,

Thank you for the query.

Please refer below FAQ

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1391522/faq-am625-am623-am620-q1-am64x-am243x-am62ax-am62px-am62d-q1-am62l---bootmode-implementation-without-isolation-buffers

Additional inputs:

(4) [FAQ] AM625 / AM623 / AM620-Q1 / AM64x / AM243x / AM62Ax / AM62Px / AM62D-Q1 / AM62L - Supported bootmode configurations - Processors forum - Processors - TI E2E support forums

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1414148/faq-am625-am623-am620-q1-am64x-am243x-am62ax-am62px-am62d-q1-am62l---bootmode-implementation-with-isolation-buffers-used

Regards,

Sreenivasa

0 prema R 3 months ago in reply to Kallikuppa Sreenivasa

Intellectual 920 points

Thanks Sreenivas

We would however like to retain the buffers, as it's not clear how 0 ohms can provide isolation when processor is ON. Usually, isolation resistors are mounted or made DNP to choose the functionality.

Since we don't have a separate 3.3V regulator test automation, we have connected the buffer power rails to SOC_DVDD3V3.

Please let us know if there are any concerns with our implementation.

0 Kallikuppa Sreenivasa 3 months ago in reply to prema R

TI__Guru**** 211260 points

Hello prema,

Thank you.

prema R said:
We would however like to retain the buffers, as it's not clear how 0 ohms can provide isolation when processor is ON. Usually, isolation resistors are mounted or made DNP to choose the functionality.

The isolation is provided when buffers are used since the buffers are output and just in case the bootmode inputs are set as output before the buffer is disabled.

When you are not using the buffers, there is no need for isolation since there is no concern of contention.

The 0R are provided for isolating the alternate function incase you see some issues with processor boot.

prema R said:
Since we don't have a separate 3.3V regulator test automation, we have connected the buffer power rails to SOC_DVDD3V3.

Can you confirm the power architecture you are using.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 211260 points

Hello Prema,

Please note the below:

Boot mode input buffers are optional for normal bootmode use case and are provided on the EVM to support test automation.

Regards,

Sreenivasa

0 prema R 3 months ago in reply to Kallikuppa Sreenivasa

Intellectual 920 points

Understood Sreenivas, So we will go ahead in removing the buffers. Attaching the power architecture as you had asked.

power_architecture.pdf

0 Kallikuppa Sreenivasa 3 months ago in reply to prema R

TI__Guru**** 211260 points

Hello Prema,

Thank you.

Glad you have been able to optimize the design.

With the PMIC used, it should be Ok to connect the 3.3V_VSYS voltage as pullup for the bootmode input pullups.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 211260 points

Hello Prema,

Quick question:

Are you planning to use the partial IO mode capability of the SOC.

If YES the VDD_CANUART and the VDDSHV_CANUART needs to be connected to an always ON supply.

Regards,

Sreenivasa

0 prema R 3 months ago in reply to Kallikuppa Sreenivasa

Intellectual 920 points

Hi Sreenivas

Could you please explain partial IO mode.

And please accept my connection request, so that I can share the schematics with you

0 Kallikuppa Sreenivasa 3 months ago in reply to prema R

TI__Guru**** 211260 points

Hello Prema,

Thank you.

Can you confirm if you need to implement low power capability.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 211260 points

Hello Prema,

prema R said:
And please accept my connection request, so that I can share the schematics with you

You can share the schematics over private chat.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 211260 points

Hello Prema,

Please refer below:

https://www.ti.com/lit/wp/sprad41/sprad41.pdf

https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/latest/exports/docs/linux/Foundational_Components/Power_Management/pm_low_power_modes.html

https://www.ti.com/lit/an/spradg1/spradg1.pdf

https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/11_01_05_03/exports/docs/linux/Foundational_Components/Power_Management/pm_wakeup_sources.html

e2e.ti.com/.../faq-am62p-how-to-measure-wakeup-latency-for-low-power-modes-on-am62x-a-p

Regards,'

Sreenivasa

0 prema R 3 months ago in reply to Kallikuppa Sreenivasa

Intellectual 920 points

Hi Sreenivas

No, low power mode not required. The HMI is powered via an external 24V DC adapter derived from the mains.

0 Kallikuppa Sreenivasa 3 months ago in reply to prema R

TI__Guru**** 211260 points

Hello Prema,

Thank you.

In case you have used an always ON supply and generated VDD_CANUART supply following the SK schematics, please delete the LDO and connect the supply that is connected to VDD_CORE to VDD_CANUART

You can connect the VDD_CANUART to any valid IO supply depending on the levels the IOs are configured or connected to.

Regards,

Sreenivasa

0 prema R 3 months ago in reply to Kallikuppa Sreenivasa

Intellectual 920 points

Hi Sreenivas

We have not used LDO for VDD_CANUART. we have connected it to VDD_CORE. I'll share the schematics over a private chat.

0 Kallikuppa Sreenivasa 3 months ago in reply to prema R

TI__Guru**** 211260 points

Hello Prema,

Thank you.

I assume the VDDSHV_CANUART is connected to one of the fixed IO supply.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 211260 points

Hello Prema,

Make sure you use the below available design collaterals to perform a self-review (focus on the collaterals in bold) before sharing the schematics.

Recommended References for review and design of custom board
AM62X
TI.com product page
www.ti.com/.../AM625
www.ti.com/.../AM623
www.ti.com/.../AM620-Q1
www.ti.com/.../AM625-Q1

Collaterals
AM62x Sitara Processors datasheet (Rev. B)
www.ti.com/.../sprsp58

AM62x
Processors Silicon Revision 1.0 Texas Instruments Families of Products spruiv7b
www.ti.com/.../spruiv7

AM625SIP – AM6254 Sitara Processor with Integrated LPDDR4 SDRAM datasheet (Rev. A)
www.ti.com/.../sprsp98

AM62x Sitara Errata (Rev. F)
www.ti.com/.../sprz487
Hardware Design Considerations
www.ti.com/.../sprad05
Hardware Design Considerations for Custom Board Using AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP Processor (Rev. E)
AM62x, AM62Lx DDR Board Design and Layout Guidelines
www.ti.com/.../sprad06
Schematic Design and Review Checklist for AM62x processor family
www.ti.com/.../sprado3
AM625, AM623, AM620-Q1, AM625-Q1, AM625SIP Processor Family Schematic, Design Guidelines and Review Checklist (Rev. B)
Schematic Design and Review Checklist combined for sitara processor families
www.ti.com/.../sprad21
AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Family Schematic, Design Guidelines and Review Checklist (Rev. I)

AM62x, AM62Ax, AM62Px, AM62Lx Spread-Spectrum Clocking
www.ti.com/.../spradk1
This document describes how EMI reduction is achieved when using the Display Parallel Interface (DPI) with
a 24-bit RGB data output to modulate the pixel clock frequency using SSC. The method applies to AM62x,
AM62Ax, AM62Px, and AM62Lx system-on-chip (SoC) designs.

AM62x Schematic checklist
e2e.ti.com/.../faq-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---schematics-review-checklists

AM62x Schematic self-review
e2e.ti.com/.../faq-am625-am623-am625sip-am620-q1-am625-q1-design-recommendations-custom-board-hardware-design---custom-board-schematics-self-review
e2e.ti.com/.../faq-am625-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---list-of-errors-observed-during-customer-schematics-review
e2e.ti.com/.../faq-am625-am623-am62a-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-sk-schematics-updates-for-design-update-note
e2e.ti.com/.../faq-am625-am623-am62a-am62p-am62d-q1-am64x-am243x-design-recommendations-custom-board-hardware-design---queries-related-to-soc-data-sheet-pin-attributes
e2e.ti.com/.../faq-am62x-am64x-custom-board-hardware-design-how-to-handle-used-unused-pins-peripherals-e-g-gpios-serdes-usb-csi-mmc-emmc-sd-card-csi-oldi-dsi
e2e.ti.com/.../faq-am625-am623-am62l-am62a-am62d-q1-am62p-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-soc-peripherals-and-ios-connection-when-not-used

Frequently Asked Questions FAQs for master list of FAQs for all AM6 processor families and AM62x processor family
e2e.ti.com/.../faq-custom-board-hardware-design---master-complete-list-of-faqs-for-all-sitara-processor-am62x-am64x-am243x-am335x-families
e2e.ti.com/.../faq-am625-am623-am625sip-am625-q1-am620-q1-custom-board-hardware-design---faqs-related-to-processor-collaterals-functioning-peripherals-interface-and-starter-kit

Frequently Asked Questions FAQs for schematics D-Note, R-Note design notes
e2e.ti.com/.../faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-schematics
e2e.ti.com/.../faq-am625-am623-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62b-p1-schematics
e2e.ti.com/.../faq-am625-q1-am620-q1-custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62-lp-schematics
e2e.ti.com/.../faq-am625sip---custom-board-hardware-design---design-and-review-notes-for-reuse-of-sk-am62-sip-schematics

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 211260 points

Hello Prema,

Can you confirm if you are working with any of the TI sales or Support team or team members for this project?

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 211260 points

Hello Prema,

I have not hear from you.

In case you need to reach out to TI support in case you are already not working, please send an email to reach2ti_india@list.ti.com. Our India MM team is on the mailing list

Regards,

Sreenivasa