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Original question:

TDA4VM: BIST initialize DRAM doesn't work normally

DRA829J: Issue with LPDDR4 partial priming using BIST

Dmitry Tuykov
Expert 1281 points

Part Number: DRA829J

Hello TI-Team,

we're going to use BIST to prome the LPDDR4 and we have a similar issue, which is described in this E2E thread: TDA4VM: BIST initialize DRAM doesn't work normally - Processors forum - Processors - TI E2E support forums.

BIST works pretty well in two cases:

  • partial / complete memory priming while inline ECC is not enabled
  • complete memory priming while inline ECC is enabled

But we have an issue when we try to prime memory portion by portion, having inline ECC enabled. Setting up start address and number of address bits I see that it results in priming region located at another address and having another size. I can imagine that it's a result of different to CPU / DMA path BIST accesses memory.

But referencing the thread above, answer from TI was quite primising and sounded to be like there is a patch planned to be introduced in upcoming PDKs. But has it happened already, is there any pending update?

Thanks,
Dmitry

  • 0
    TI__Guru**** 170580 points

    Hello Dmitry,

    Is this something that you have tried with latest 11.1 SDK?

    Can you share all the logs?

    - Keerthy

  • 0 in reply to Keerthy J
    Expert 1281 points

    Hi Keerthy,

    no, I tested with my code accessing BIST related registers directly.

    If you could navigate me a bit to the respective code in the PDK, I will compare with what I did.

    Thanks,
    Dmitry

  • 0
    TI__Mastermind 44190 points

    Hi Dmitry,

    Dmitry Tuykov said:
    But we have an issue when we try to prime memory portion by portion, having inline ECC enabled. Setting up start address and number of address bits I see that it results in priming region located at another address and having another size. I can imagine that it's a result of different to CPU / DMA path BIST accesses memory.

    When you turn on ECC, the system to DDR address map is distorted (because ECC codes are stored in blocks in-between data blocks, and these ECC codes are hidden from the system view such that DDR data space appears continuous , benefitting software).  However, the DDR controller BIST ALWAYS accesses the DDR address.

    Also, using BIST does not go through the ECC logic, which means you need to ensure that BOTH ECC data and ECC codes are set to 0x0. 

    Regards,
    Kevin

  • 0 in reply to Kevin S
    Expert 1281 points

    Hi Kevin,

    do I get it right, that I cannot 'calculate' physical range to be primed by BIST such a way that after enabling ECC the desired 'logical' range is primed?

  • 0 in reply to Dmitry Tuykov
    TI__Mastermind 44190 points

    My comment was to indicate that if you use BIST to prime the first 1 MB of DDR, you cannot confirm that 1MB of DDR was written by BIST when ECC is enabled. This is because:

    • Within the 1MB physical block of LPDDR4, portions of this space are used for 'data' and portions of this space are used for 'ecc codes'.
    • The 'ecc code' portions of memory are not visible from the system view (i.e, from the A72, R5, DSP, etc.). 

    Thus when use have ECC enabled and you use BIST to initialize 1 MB of DDR, it likely appears (from CPU view) that only ~ 900 KB were initialized. 

    What is an example region you are trying to protect. (what is the system address range?)

    Regards,
    Kevin