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AM62P: AM62P: xSPI bootmode clarification

Fan Bomiao
Prodigy 250 points

Part Number: AM62P
Other Parts Discussed in Thread: SYSCONFIG

Hi,
 
I am using xSPI bootmode to implement boot time optimzation and I have found several problems.
I. Referring to Table 5-8 in TRM, I think there are three modes for xSPI: 1S, 8D and SFDP. 
Based on the Figure 5-5 in TRM, I think the boot process will not be affected whatever bootmode pin 7 and 8 are configured when bootmode pin 9 is set 1. I would like to confirm whether my comprehension above is correct. 
screenshot-20251219-131451.png
II. I have done a small experiment with arranging bootmode pins [7], [8], [9] and the result is shown as a table below. From the table, I found the ROM boot time could be reduced when SFDP is enabled, which is a valuable information I have confirmed one week ago from E2E. But I also found the boot process failed under 8D mode, which is contrary to the statements in TRM saying " For 8D-8D-8D mode of operation, the ROM will issue a Fast Read command (0x0B or 0xEE, depending on BOOTMODE signal), followed by a 32 bit (4 byte) address (the starting address is all zeros)". For this circumstance, I have flashed a SBL1 image and I set a GPIO low at the beginning of main() function, similar to TI's SBL time measurements tutorial (4.1.12. Boot Time Optimizations — Processor SDK AM62Px Documentation ). But the test pin I have measured is always high so I think the software is stuck in ROM boot.
screenshot-20251219-113820.png 
 
III. Referring to Figure 5-5 in TRM, it says the operating frequency is 25MHz when SFDP is enabled. However, the OSPI_CLK I have measured during ROM boot is 5MHz. The test pin is shown below. 
screenshot-20251219-140551.png
I could also attach the oscilloscope screenshots below. I wonder whether this phenomenon is normal during ROM boot. If the answer is negative, what should I do to help OSPI_CLK to reach 25MHz during ROM boot.
screenshot-20251217-135453.png
Regards,
Bomiao
 
 
 
  • 0
    Prodigy 250 points

    Btw, the hardware I use is EVM and the MCU+SDK I am using is 11.01.01.08.

  • 0 in reply to Fan Bomiao
    TI__Guru 57835 points

    Hello Fan,

    When using xSPI but without SFDP enabled, the ROM expects the 4 byte address to be sent as per the bootmode description. You can read this under the xSPI bootloader description from the TRM.

    Now the flash, when it undergoes a PORz and ROM starts booting, is in a reset state which means it is in 3 bytes addressing state.

    This also means that the NVCR is actually configured by default to 3 byte addressing, and hence this value gets copied to VCR itself.

    So in order to boot purely in 8D-8D-8D, I see that you would need to set NVCR to 4 byte addressing such that upon PORz, the reset value is 4 byte addressing itself, and hence the booting will take place.

    One the frequency question which you have:

    Can you please recheck if the frequency is actually 5 MHz or you measured it incorrectly. Please confirm on this front.

    Looking forward to your response.

    Kind Regards,

    Vaibhav

  • 0
    TI__Guru 57835 points
    Fan Bomiao said:
    I think the boot process will not be affected whatever bootmode pin 7 and 8 are configured when bootmode pin 9 is set 1

    Yes your understanding is correct, it will be a NO CARE, when SFDP is enabled, but it is always a good practise to have them at 0, reason being we have not validated for numerous boot cycles if having 7, 8 as any random value when SFDP is enabled does not cause any issue. So in theory yes 7, 8 will be a NO CARE, but good to set it to 0.

  • 0 in reply to Vaibhav Kumar
    Prodigy 250 points

    Hi Vaibhav,

    Vaibhav Kumar said:
    Can you please recheck if the frequency is actually 5 MHz or you measured it incorrectly. Please confirm on this front.

    I have double-checked the measurement of 5MHz and I think my measurement is correct. I could attach the relevant screenshots below.

     

    Regards,

    Bomiao

  • 0 in reply to Fan Bomiao
    TI__Guru 57835 points

    Hi Fan,

    Thanks for mentioning this. I am reviewing this and will get back to you in sometime.

    Regards,

    Vaibhav

  • 0 in reply to Vaibhav Kumar
    TI__Guru 57835 points

    Hi Bomiao,

    You should be measuring the R415, and not R410 to see the proper clock.

    Regards,

    Vaibhav

  • 0 in reply to Vaibhav Kumar
    Prodigy 250 points

    Hi Vaibhav,

    For measuring the signal of OSPI_CLK, I think R415 and R401 are equivalent. Now I could get 50MHz when measuring the OSPI_CLK during ROM and SBL 1 after adjusting the parameter of oscilloscope. Sorry about my mistakes.

    I have further questions about configuring the OSPI_CLK in Sysconfig. In example project "sbl_ospi_linux_stage1_am62px-sk_wkup-r5fss0-0_nortos_ti-arm-clang", the OSPI driver is enalbed with its clock set as 166666666Hz and input clock divider set as 4. The related screenshot is attached below. Does this means the OSPI_CLK is 41.6MHz during SBL1? If so, I think there is a contradiction because the OSPI_CLK I measuring during SBL1 is 50MHz. 

    Additionally, I wonder the relationship between the OSPI_CLK configured by Sysconfig in SBL1 and the clock tree of OSPI.  I want to ask which specific part of OSPI clock tree corresponds to the input clock frequency 166MHz along with clock divider mentioned in Sysconfig. I attached the screenshot of OSPI clock tree below.

    Regards,

    Bomiao

  • 0 in reply to Fan Bomiao
    TI__Guru 57835 points

    Hello,

    Glad to see you get 50 MHz on the oscilloscope after setting the correct configurations.

    For the SBL, in stage 1 and stage 2, we just do reading.

    Please refer this OSPI PHY Tuning FAQ, in general to gain awareness on what is PHY Tuning and how it improves the FLASH Read Speed.

    FAQ:  [FAQ] AM62x, AM62Ax, AM62Px, AM62D-Q1, AM64x, AM243x: OSPI Phy Tuning Algorithm 

    This will answer your query.

    Kind Regards,

    Vaibhav

  • 0 in reply to Fan Bomiao
    TI__Guru 57835 points

    Please read this after you have referred the FAQ:

    You will see that the 166 MHz is the speed, and the clock divider is bypassed, in this case 4 is bypassed as PHY is checked.

    Hope this helps.