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AM62L: Distorted eMMC HS200 Clock Waveform

Kunal Barot
Prodigy 70 points
Part Number: AM62L
Other Parts Discussed in Thread: TMDS62LEVM

Hi Support Team,

Please find the attached oscilloscope capture of the eMMC clock (CLK) waveform operating in HS200 mode.

We are observing that the clock waveform appears significantly distorted and closer to a sinusoidal shape, whereas we were expecting a cleaner square-wave profile, especially at the source side. For reference:

  • HS200 clock frequency: 200 MHz

  • Series termination resistor: 22 Ohm on the CLK line

  • Scope bandwidth setting: 1 GHz

  • Probe: passive probe with spring ground to minimize ground loop effects

Given this setup, we would like your guidance on the following points:

  1. Waveform Expectation

    • Is a sinusoidal-looking clock waveform expected at HS200 speeds due to bandwidth limitations, transmission line effects, or SoC output driver characteristics?

    • At what point (SoC pin vs. eMMC pin) should the waveform be evaluated for compliance?

  2. Measurement Technique Validation

    • Is the current measurement approach (1 GHz BW, passive probe with spring ground) sufficient for HS200 signal integrity analysis, or would you recommend:

      • An active probe

      • A higher-bandwidth scope/probe

      • Differential probing or alternative measurement points?

  3. Series Resistor Impact

    • Could the 22 Ohm series resistor be contributing to the observed waveform shaping?

    • Is there a recommended value range for the CLK series resistor in HS200 mode for this SoC–eMMC combination?

  4. Layout and Routing Considerations

    • What specific PCB layout aspects should we review (trace impedance, length matching, stubs, via count, reference plane continuity) that could cause this behavior?

    • Are there known layout guidelines or reference designs we should cross-check against?

  5. Confirmation Methodology

    • What is the recommended method to distinguish between:

      • Measurement artifact

      • Acceptable high-speed signaling behavior

      • A genuine signal integrity issue requiring layout or termination changes?Are eye-diagram or mask-based checks recommended for HS200 CLK validation?

Your inputs will help us determine whether this waveform is within acceptable limits for HS200 operation or if corrective action is required at the PCB or termination level.

Looking forward to your guidance.MMC0_CLK_000.png

Best regards,
Kunal Barot

 

  • 0
    TI__Expert 5890 points

    Hello Kunal Barot,

    Thank you for your query !

    Can you show with a simple circuit diagram  GND - eMMC_CLK generator-22R-transmission line-eMMC Flash CLKIN - GND, where did you place the probe ? 

    Kunal Barot said:

    Waveform Expectation

    • Is a sinusoidal-looking clock waveform expected at HS200 speeds due to bandwidth limitations, transmission line effects, or SoC output driver characteristics?

    • At what point (SoC pin vs. eMMC pin) should the waveform be evaluated for compliance?

    With the appropriate measurement equipment, at 200 MHz, I do not expect a sinusoidal shape of the probed signal too. It shall be still displayed as a square-wave with possible distortions (such as ringing,  dips from reflections, etc.). This because of impedance mismatching caused by HW design / PCB layout design imperfections. The ground spring you use is typically recommended.

    P1. Though you mention that the used passive probe BW matches the scope BW of 1 GHz (5x 200MHz), I can't rule out that the observed sinusoidal shape might be caused by the passive probe characteristics. What is the input capacitance, resistance, ground loop self-inductance (or input impedance) of your passive probe according to the documentation ?

    Please consider the below table CL restrictions for the HS200 mode from Section, MMC0 - eMMC/SD/SDIO Interface of the AM62L Datasheet:

    For example a standard 10x passive probe may have an input capacitance of 10-20 pF which is added up to the input impedance of the scope and output impedance of the tested eMMC clock circuit. The increased equivalent RL and CL might create low-pass filtering effect which at 200 MHz makes waveform looks more like a sinusoid.

    P2. Is your passive scope probe manually adjusted for frequency compensation ? Please check if this has been done, if not sure. This may distort to some extent the captured signal shape (visibly in the plateau area). The procedure shall be explained in your oscilloscope manual.

    I think that the waveform should be evaluated at the clock input pin of the eMMC flash memory (the waveform important at the data sampling location).

    Can you please also probe the circuit straight: 

    A/ at the AM62L eMMC_CLK pin with detached 22R series resistor

    B/ at the eMMC Flash memory CLK input with attached 22R series resistor

    P3. Can you confirm that the 22R series resistor is placed as close as possible to the AM62L eMMC_CLK (output) pin ?

    Kunal Barot said:

    Measurement Technique Validation

    • Is the current measurement approach (1 GHz BW, passive probe with spring ground) sufficient for HS200 signal integrity analysis, or would you recommend:

      • An active probe

      • A higher-bandwidth scope/probe

      • Differential probing or alternative measurement points?

    I  think, that as a first step you should still try to measure the clock with your 1 GHz- oscilloscope but with an active probe if possible. Why: Active probes use a high-impedance amplifier which helps minimize the input capacitance to less than 1 pF and help capture the shape as close as possible to the real one.

    Kunal Barot said:

    Series Resistor Impact

    • Could the 22 Ohm series resistor be contributing to the observed waveform shaping?

    • Is there a recommended value range for the CLK series resistor in HS200 mode for this SoC–eMMC combination?

    I don't think it will make the square wave clock look like a sinusoid, but it may impact the slew rate of the signal - increasing the rise and fall times of the signal.

    Please allow me some time for the remaining questions. I will follow-up shortly today.

    Wish you a successful 2026 year !

    Thank you 

    Kind Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    TI__Expert 5890 points

    Hi Kunal,

    The series resistor value lies typically within the range 0R - 47R which shall be normally sufficient to compensate any impedance mismatches and caused signal reflections. Higher values may be needed in case that the eMMC clock trace has a higher impedance. It is always recommended to have a dummy 0R resistor placeholder on the PCB, to be able to place a non-dummy resistor when compensation is necessary. The "signal shape correction" typically starts with a dummy 0R resistor. You'd better keep the 0R value in case you do not observe any reflections (no ringing, no dips). Using a too high value for a series termination resistor may reduce the clock slew rate below the minimal eMMC Flash memory clock input slew rate.   

    Here is a quite informative FAQ on the eMMC Memory Interface Signal Integrity: AM62x-design-recommendations-commonly-observed-errors-during-custom-board-hardware-design-emmc-memory-interface

     Here are some MMCSD0 clock series termination related excerpts:

    A 22R or 33R- series resistor values, greater or lower values are possible depending on the clock transmission line characteristic impedance, and there is some process of testing until best value is found.

    It is correct to observe the signal with probe directly at the input of the eMMC Flash memory when series resistor selection is performed. If you observe with a probe directly at the processor eMMC clock output, you observe a step like- flat segment in the signal shape approximately at a half the power-supply level when the series resistor has compensated the impedance mismatch. While the series termination resistor is placed near the processor clock output, the effect of reflections is observed to be compensated at the receiver side.

    Regarding the reflections compensation mechanism the above FAQ specifies:

    Kunal Barot said:

    Layout and Routing Considerations

    • What specific PCB layout aspects should we review (trace impedance, length matching, stubs, via count, reference plane continuity) that could cause this behavior?

    • Are there known layout guidelines or reference designs we should cross-check against?

     The below table in the Section, MMC0 - eMMC/SD/SDIO Interface of the AM62L Datasheet  specifies propagation delay constraints common for the PCB eMMC traces that shall be respected for an eMMC HS200 mode support:  

     

    From the above FAQ:

    References to the AM62L eMMC  Datasheet and Custom board Hardware Design Recommendations, Schematic Review Checklist, Layout Design Recommendations

    Here is an FAQ on the Sitara high speed interface PCB layout topics:

    Sitara Board Layout – Links to documents for General High Speed Layout Guidelines  

    Here is an excerpt - a general high speed interface PCB routing guidance relevant for the AM64x/AM243x EMMC layout implementation (very likely to be applicable to the AM62L too).

    You can check eMMC implementation  (schematic and layout) according the TI reference design - TMDS62LEVM available here:

    TMDS62LEVM Design File Package Orcad_Allegro (Rev. D) sprcal6d

    sprcal6d_TMDS62L_AM62L32B\TMDS62LEVM Design File Package Orcad_Allegro (Rev. C)\PROC181\1_PROC181E1-1a\1_SCHEMATIC\3_PDF_Intelligent\PROC181E1-1a_SCH_With_Design_Updates..Notes_V1.0_Smart.pdf

    Regarding your point:

    "Confirmation Methodology:

    • What is the recommended method to distinguish between:

      • Measurement artifact

      • Acceptable high-speed signaling behavior

      • A genuine signal integrity issue requiring layout or termination changes?Are eye-diagram or mask-based checks recommended for HS200 CLK validation?" 

    To eliminate measurement artifacts you will need an equipment with characteristics as described in my previous answer to your question 1 and  in the mentioned FAQ :

    Acceptable high-speed signal behavior:

    After the necessary equipment is available, the next step is to evaluate the high-speed signal parameters versus the ones present in the Datasheet - the input timing requirements and output switching characteristics in the Section, HS200 Mode of the AM62L Datasheet. The actual signal levels versus the min and max specified for the eMMC pins SDIO type- buffers covered in Section, SDIO Electrical Characteristics of the AM62L Datasheet. 

    An eye diagram with a test mask can be a good method to faster examine HS200 signal integrity of the eMMC clock regarding the average jittering, noise vulnerability, minimal and maximal rise and fall times, overshoot and undershoot and  max/min electrical levels over time.

    In addition: Do you currently have any real concerns regarding the eMMC system behavior in the HS200 mode (errors occur more frequently, data corruption, etc.) ?

    I hope this clarifies !

    Thank you 

    Kind Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    Prodigy 70 points

      Currently no performance issue observe with eMMC. we also take measurement with Series resistor (R1) changed to Zero Ohm. See Below

  • 0 in reply to Kunal Barot
    TI__Expert 5890 points

    Hi Kunal,

    I think with 0R there are still some small reflections visible in the plateau of the pulses at eMMC flash memory side  (little overshoot and undershoot < 10%). I think that it makes sense of an improvement. Would you please try with R1=4.7R or 10R series resistors and test for performance issues respectively. Please try to probe the clock at the eMMC memory end - the target is to achieve a balance between minimal overshoots/undershoots and minimal rise/fall times.

    Thanks

    Kind Regards,

    Anastas Yordanov   

  • +1 in reply to Anastas Yordanov
    TI__Expert 5890 points

    Hi Kunal,

    I haven’t heard from you for almost 3 weeks, so I’m assuming you were able to resolve your issue. If this isn’t the case, please click the "This did NOT resolve my issue" button and reply to this thread with more information. If this thread locks, please click the "Ask a related question" button and in the new thread describe the current status of your issue and any additional details you may have to assist us in helping to solve your issues.

    Regards,
    Anastas Yordanov