Additionally for relevant peripherals, trace length and matching requirements are defined in the respective Timing Conditions table found in the timing sections of the datasheet.

There is no relationship between CK and Data groups, so it is not necessary to maintain any length differences.

AM62A3: DDR layout guidelines vs AM62A EVM

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1332846/am62a3-ddr-layout-guidelines-vs-am62a-evm?tisearch=e2e-sitesearch&keymatch=board%25252520layout%25252520guidelines#

SK-AM62: LPDDR4 HDI Layout guideline

(+) SK-AM62: LPDDR4 HDI Layout guideline - Processors forum - Processors - TI E2E support forums

AM623: DDR4 Board Design and Layout Guidance

(+) AM623: DDR4 Board Design and Layout Guidance - Processors forum - Processors - TI E2E support forums

We do not require VTT termination for point to point designs with only one DDR4 device. This is what the AM62x SK EVM demonstrates

Maybe they are they looking for package delays? This is in the DDR layout guidelines: https://www.ti.com/lit/pdf/sprad06 in section 5

What the customer wants to know is below parameters.
a) CMD/ADD/CTRL signal delay(min/max) against CLK signal
b) DQS signal delay(min/max) against CLK signal
c) DQ signal delay(min/max) against DQS signal

The background of the question is;
The customer thinks total delay consist of (delay of PCB) + (package delay) + (above parameters a/b/c)

The signal delays are optimized during training and will most likely be different with every initialization cycle. The hardware training algorithms will adjust the relative skews of the signals for optimal timing. As long as you provide the correct DDR configuration using the DDR Register Configuration tool, https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM62x, the controller/PHY training procedure will generate optimal skews across the signals in question. Signal delay values that are applied as calculated during training are only available as encoded values and do not represent anything the customer can use.

Note that if you only have one DDR4 device with only one load on the addr/ctrl signals, then VTT termination is not required (an update to the app note to reflect this is pending). Thus you wouldn't need to worry about AT length.

The document states that when using a single DDR4 chip, VTT termination is optional. So, could you please explain what the differences are between having VTT and not having it, and whether this has any impact on the performance of DDR? Would there be any potential problems if the VTT connector is not designed?

VTT termination is mainly for signal integrity, it does not affect functional performance of DDR in regards to bandwidth or latency. If you're meaningfully concerned about signal integrity for your board, you should follow the document you referenced (DDR layout guidelines for AM62L https://www.ti.com/lit/pdf/sprad06) and consider performing board level simulations to verify signal integrity. You can also reach out to the memory vendor of your DRAM to seek additional recommendations as well.

But I also like to know if the pin package delay can be ignored without issues?

Also, should the pin package delay of the DDR chip in use be considered as well?

Pin package delay consideration should not be necessary. During the training process, there is per-bit deskew which can compensate for package length mismatches. As long as you match pin to pin on board according to the skews in the appnote, the training will take care of optimizing skews across byte lanes and ctrl/addr signals

AM6412: Layout Review of AM6412 and DDR

(+) AM6412: Layout Review of AM6412 and DDR - Processors forum - Processors - TI E2E support forums

No, sorry, we don't get into layout reviews or simulations with customers. We can do a schematic review if needed. Please refer to the following for layout guidelines: https://www.ti.com/lit/pdf/sprad06

For simulation, you can check section 3 of this app note. Although it is for a different device, a lot of the information in section 3 will apply to AM62x: https://www.ti.com/lit/pdf/sprad66

increasing trace impedances to 50/100 should be ok, there may be some adjustment that need to be made to the drive strength or termination values, but those are software configurable. Board SI simulations are encouraged to ensure proper signal integrity and come up with those optimized values. Be sure to follow all the guidelines in AM62x DDR Layout Guidelines app note: https://www.ti.com/lit/pdf/sprad06

DRA821U: LPDDR4 layout simulation

(+) DRA821U: LPDDR4 layout simulation - Processors forum - Processors - TI E2E support forums

As mentioned in the application note - the S-param inspection is not pass/fail, but rather a guide to help identify possible issues. The pass fail simulations are the eye diagrams.

AM625: Layout guidelines for MCASP interface

(+) AM625: Layout guidelines for MCASP interface - Processors forum - Processors - TI E2E support forums

MCASP is a standard interface provided on multiple family of TI devices. Please refer below. Only requirement is to add series resistor for the clock and other signals.

https://www.ti.com/lit/an/sprack0/sprack0.pdf

https://www.ti.com/lit/an/sprace0a/sprace0a.pdf

AM69A: Is there layout guide for VOUT0_DATA0~23, HDMI, RGMII, eMMC, SD?

(+) AM69A: Is there layout guide for VOUT0_DATA0~23, HDMI, RGMII, eMMC, SD? - Processors forum - Processors - TI E2E support forums

No - we do not have any layout guide for the interfaces mentioned. We have 2 hardware references you can use for guidance: SKAM69 and J784S4XEVM. I also recommend reviewing the Jacinto7 High Speed Guidelines application note (Link). It includes some good general recommendations for PCB routing.

Section 1 of the previously reference document (Jacinto7 High Speed Guidelines) provides general PCB routing recommendations for all high speed signals - including the interfaces you mentioned. Recommendations include impedance control, use of solid GND planes, via suggestions, etc.

VOUT, RGMII, eMMC, and SD interfaces are sourced from LVCMOS drivers. They are recommended to be routed with 50-ohms SE traces. The processor web page includes IBIS models to simulate these interfaces with your PCB to determine any possible signal integrity/coupling issues (dependent on you PCB board materials, via plan, and overall trace lengths)

TDA4VE-Q1: MMC layout guidelines

(+) TDA4VE-Q1: MMC layout guidelines - Processors forum - Processors - TI E2E support forums

The SD and JEDEC industrial specifications provide guidelines on electrical and mechanical connections of the card
and controller for reliable operation. You must follow these guidelines to ensure proper functionality.
TI offers a schematic checklist as well. For more information on the checklist – or to submit your board layout
files for review with TI – approach your local Field Application Engineer to understand the review submission
process.

A few of the recommended signal integrity best practices include:
• Separate routing layers with GND layers.
• Avoid gaps in ground plane between source and load.
• Wherever a signal goes through a via, have a return GND via very close (within a few mm).
• Avoid cross-talk/coupling. Do not route two signals directly above or below each other.
• Avoid cross-talk/coupling. Route traces with spaces between traces that are 2-3X the trace width.
• Avoid stubs. Have zero stubs on traces.
• Ensure signals are monotonic at inputs
• Ensure impedance match

How to handle skew compensation for DPHY/CSI, PCIe/DDR4?

(+) TDA4VM: High speed interface layout (spraar7) : How to handle skew compensation for DPHY/CSI, PCIe/DDR4? - Processors forum - Processors - TI E2E support forums

That is my design - "the other pair's" bulge is comming outside of the picture (due to the via's space constraint)

2.) Could I finally repeat if I got you right:

a.) All high speed signals (e.g. PCIe, CSI/DPHY) have no "internal" (within chip package) skew and hence start at the balls with zero skew.

b.) If I want to address TI's recommendations I've to add the length on the pcb as of spraar7i:

2a) Correct - assume package has zero skew

2b) Correct - minimize impedance discontinuity by adjusting skew mismatches at single/few locations.

AM62P-Q1: Z-impedance for Layout of different function module

(+) AM62P-Q1: Z-impedance for Layout of different function module - Processors forum - Processors - TI E2E support forums

Sitara Processor Power Distribution Networks

https://www.ti.com/lit/an/sprac76g/sprac76g.pdf

High-Speed Interface Layout Guidelines

https://www.ti.com/lit/an/spraar7j/spraar7j.pdf

Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines

https://www.ti.com/lit/an/spracp4a/spracp4a.pdf

AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines

https://www.ti.com/lit/an/sprad66b/sprad66b.pdf

Jacinto7 AM6x/TDA4x/DRA8x LPDDR4 Design Guidelines

https://www.ti.com/lit/an/spracn9f/spracn9f.pdf

TDA4VH-Q1: LPDDR4 layout

(+) TDA4VH-Q1: LPDDR4 layout - Processors forum - Processors - TI E2E support forums

1) The table showing the performance impacts from different PCB stack-ups was originally done from TDA4VM. However - TDA4VH uses same/similar LPDDR4 IP and thus should expect similar results.

2) TI EVMs targeted a slightly lower impedance (33-ohms vs 35-ohms) due to the difficulty achieving the 2x impedance for the T-branches (66-ohms vs 70-ohms). Depending on the specific PCB trace width restrictions, it can be difficult to achieve the higher impedances. The recommendation is to get as close as the design allows (to 2x the base impedance), and the simulations will confirm if it is close enough. Lowering the base impedance lowers the T-branch impedance - allowing the achieved impedance closer to target.

TDA4VM-Q1: TDA4VM-Q1's High speed signal layout Guidelines.

(+) TDA4VM-Q1: TDA4VM-Q1's High speed signal layout Guidelines. - Processors forum - Processors - TI E2E support forums

Jacinto 7 High-Speed Interface Layout Guidelines

[FAQ] AM62L: DDR4 guidelines for impedance values

(+) [FAQ] AM62L: DDR4 guidelines for impedance values - Processors forum - Processors - TI E2E support forums

Then higher impedance is okay.

In lightly loaded signals, such as point-to-point signaling; 50 to 60 ohm single-ended and 80 to 100 ohm differential are common.

Keep in mind tolerance of manufacture may add or subtract 10% to the actual impedance.

It is easier to lower trace impedance by using wider traces than make traces thinner as they sometimes become too thin for manufacture. Dielectric thickness in the stack-up (distance from reference plane) is the other way to change impedance.

Additional inputs

If there are multiple DRAMs and the command/address hit multiple loads, then it may be required to use lower impedance - 35 to 45 ohm single-ended and 70 to 100 ohm differential.

AM6442: DDR Design and Layout Questions

(+) AM6442: DDR Design and Layout Questions - Processors forum - Processors - TI E2E support forums

The requirements are from pin to pin. You do not need to consider the package pin delays, as the training algorithm will compensate for any further mismatch caused by the package

AM6412: DDR4 unused pins

(+) AM6412: DDR4 unused pins - Processors forum - Processors - TI E2E support forums

AM6442: DDR board design

(+) AM6442: DDR board design - Processors forum - Processors - TI E2E support forums

We typically don't provide that information as the IBIS model should include coupled package RLC parasitics which are far more accurate than delay estimates.

AM4378: AM4378 Layout Guidelines

(+) AM4378: AM4378 Layout Guidelines - Processors forum - Processors - TI E2E support forums

DDR layout guidelines are available in the AM437x device datasheet in the TIming and Switching Characteristics section, and RGMII details are available in the High-Speed Interface Layout Guidelines (SPRAAR7). We do not provide any specific layout guides for the other interfaces. Standard layout practices should be followed.

AM5706: Layout to minimize layers

(+) AM5706: Layout to minimize layers - Processors forum - Processors - TI E2E support forums

AM62A7: Nanya DDR layout guidance - dual die, chip select signals

(+) AM62A7: Nanya DDR layout guidance - dual die, chip select signals - Processors forum - Processors - TI E2E support forums

Hi Brian, you connection looks correct. We have shared address/CKE/CK signals for the two channels, so those signals need to be t-branched on the board to each channel on the memory. The CS signals, however, are point to point. I think this still meets Nanya datasheet statement, as i think the statement is just requiring a separate signal for each channel (ie, you don't need to t-branch the CS signal).

It looks like your device is dual-die, dual channel, single rank. So each channel is in a separate die

What you have designed should be operational. You would need to use the DDR register configuration tool: https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM62Ax to configure the DDR appropriately.

Based on this configuration, should the customer be configuring 1 or 2 chip selects in Sysconfig? It's a little confusing based off of the terminology shared in the Nanya datasheet, which I can share offline if needed.

it is single rank, so you should configure for 1 chip select

PROCESSOR-SDK-DRA8X-TDA4X: TDA4x DDR4 Layout Guidelines

(+) PROCESSOR-SDK-DRA8X-TDA4X: TDA4x DDR4 Layout Guidelines - Processors forum - Processors - TI E2E support forums

The PCB design is CRITICAL to achieve full data rate of the LPDDR4 interface. Yes - the guidelines provide an example stack-up including which layers to route power and signals. This recommendation is to help improve both signal and power integrity - both of which are critical for LPDDR4. All of the guidelines sections are important - including the simulation section. We strongly recommend 3D simulations be run on PCB design to help ensure successful design.

TDA4VP-Q1: TADA4VP-Q1：High-Speed interface and LPDDR4 design guidelines questions.

(+) TDA4VP-Q1: ADA4VP-Q1：High-Speed interface and LPDDR4 design guidelines questions. - Processors forum - Processors - TI E2E support forums

AM67: Why the AM67x EVM LPDDR layout impedance control have different setting?

(+) AM67: Why the AM67x EVM LPDDR layout impedance control have different setting? - Processors forum - Processors - TI E2E support forums

The data bytes are routed at 40SE and 80DIFF. The clock and control interfaces are routed at lower impedances due to the T-branch portions of the traces.

The recommendation is to double the impedance at the branch location, meaning this requires impedances of 80SE and 160DIFF - likely not supported by your PCB stack-up. For this reason, we recommend your T-branch segments get as close as possible to the desired impedance and then perform simulations to see the impact. For our designs, we lowered the the traces to 33SE and 66DIFF. The T-branch segments targets are now 66SE and 132DIFF. Again - our PCB stackup can reach those targets either, but the difference from target to actual is less using the lower impedances.

TDA4VE-Q1: processor layout design

(+) TDA4VE-Q1: processor layout design - Processors forum - Processors - TI E2E support forums

The Jacinto7 LPDDR4 Layout Guidelines (link) includes some simulation results for with and without back-drill. Those simulations show that the longer via stubs can impact maximum frequency of interface. There are other mechanism - like board thickness - that can also impact the length of via stubs. Our recommendation is to limit the via stub lengths and back-drilled vias is one approach to doing that.

AM62P: the guideline of LPDDR4 simulation

(+) AM62P: the guideline of LPDDR4 simulation - Processors forum - Processors - TI E2E support forums

i would say if they can pass simulations with a certain impedance, then they should use that for silicon. They should still perform memory stress tests across temp to ensure robustness.

Since memories only have one setting for CA/CS, we choose 80ohm. Then since CS is point to point, CS driver is set to 80ohm. Since CA signals are T-branched, CA driver is set to 40ohm, and because of the T-branch, each branch would then be 80ohm. This combination provides the best chance for impedance matching.

AM62P-Q1: PCB material for LPDDR4 usage

(+) AM62P-Q1: PCB material for LPDDR4 usage - Processors forum - Processors - TI E2E support forums

standard PCB material can be used. Please follow the guidelines here: https://www.ti.com/lit/pdf/sprad66

T-branching is required for the CA lines. Please follow the guidelines in the app note. Fly-by topology is not allowed.

AM623: What is the maximum memory bytes of LPDDR4 that can be used?

(+) AM623: What is the maximum memory bytes of LPDDR4 that can be used? - Processors forum - Processors - TI E2E support forums

Regarding the LPDDR4 connection, see
The [AM62x data sheet] (P1/263) states 4GBytes with LPDDR4, but the [AM62x, AM62Lx DDR Board Design and Layout Guidelines] (P22/44) states Max2GBytes. Which is correct?
[AM62x, AM62Lx DDR Board Design and Layout Guidelines] (P22/44) states that it is possible to connect the Dual specification with Single.
In this case, is it necessary to process the pins of the other memory area of LPDDR4?

it is technically possible to get 4GB of LPDDR4 with AM62x, however, as noted in the Layout guidelines, you would have to use a dual rank, dual channel LPDDR4 and only connect 1 rank to avoid splitting the data bus on the board. Thus, you would not be able to access half of the memory.

So the layout guidelines suggests that if you are needing more than 2GB of memory, you should use DDR4.

When using 4GB(Dual) of LPDDR4, do I need to process unused pins?

you can leave most of the unused pins unconnected. The unused DQS signals on the memory should be pulled to opposite polarity (ie, DQS_t pulled low, DQS_c pulled high) with a 1K resistor

PROCESSOR-SDK-AM62X: USB VBUS Design Guidelines

(+) PROCESSOR-SDK-AM62X: USB VBUS Design Guidelines - Processors forum - Processors - TI E2E support forums

all the VBUS stages (different threshold voltages) are defined in the USB2.0 Specifications

AM3359: Layout guideline

(+) AM3359: Layout guideline - Processors forum - Processors - TI E2E support forums

DDR design guidelines are given in section 7.7.2 of the AM335x Datasheet Rev. J. Other than that there are some general documents that you can refer:
www.ti.com/.../scaa082a.pdf
www.ti.com/.../spraar7h.pdf
www.ti.com/.../sprac76c.pdf

There are no specific requirements for AM335x other than these.

AM3358: PCB layout guidelines

(+) AM3358: PCB layout guidelines - Processors forum - Processors - TI E2E support forums

DDR layout guidelines can be found in section 7.7.2.3 of the AM335x Datasheet Rev. K.

For decoupling capacitors please refer to section 5.9. General PDN guidelines are available here: http://www.ti.com/lit/an/sprac76c/sprac76c.pdf

High-speed interface layout guidelines can be found here: http://www.ti.com/lit/an/spraar7h/spraar7h.pdf

Please note that we do not offer PCB layout reviews or SI analysis for Sitara devices.

66AK2H14: XFI and Hyperlink Layout Guidelines

(+) 66AK2H14: XFI and Hyperlink Layout Guidelines - Processors forum - Processors - TI E2E support forums

Have a look at the Hardware Design Gudie for Keystone devices:
www.ti.com/.../sprabv0.pdf
As well as the SerDes Implementation Guide for Keystone ( devices:
www.ti.com/.../sprabc1.pdf

AM5728: PCIe Layout

(+) AM5728: PCIe Layout - Processors forum - Processors - TI E2E support forums

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/560657/am335x-clkout1-layout/2053103

There are no special design guidelines for CLKOUT1 layout. You can follow the general guidelines for high-speed layout: www.ti.com/.../scaa082.pdf

Make the trace impedance approximately 50 ohms and use a 22-33 ohm series termination resistor located as close as possible to the AM335x pin. The reflection that returns from the far-end of the non-terminated transmission line will be mostly absorbed by the series termination resistor and source impedance of the output buffer.

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 3 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 198259 points

PCB Layout Guidance for Functional Safety Feature

(+) DRA829V: PCB Layout Guidance for Functional Safety Feature - Processors forum - Processors - TI E2E support forums

Below are key guidelines for ensuring the safety and reliability of your system.

1. Power Supply and Ground Design

Separate Power Rails: Main Domain and MCU Domain should operate independently with separate power rails. Critical safety functions should maintain power even in fault conditions, and the power supply should be designed to avoid interference between domains.
Power Filtering and Protection: Add filtering and protection circuits to the power supply to prevent noise and abnormal conditions that could affect system operation.
Ground Separation: Physically separate the ground planes for Main Domain and MCU Domain, or use isolation techniques to reduce electrical interference. Grounding strategies must ensure the safety of both domains during fault conditions.

2. Reliable Data Transmission

Isolated Data Paths: Ensure that data paths between the Main Domain and MCU Domain are isolated to allow independent operation. Error detection mechanisms, such as CRC (Cyclic Redundancy Check), can be used to ensure reliable data transmission.
Redundant Signal Paths: For critical data, use redundant signal paths. In case of failure in one path, data can be transmitted through the other, increasing the system's fault tolerance.

3. Safe Reset and Fault Handling

Hardware Reset Circuit: Design hardware reset circuits to safely recover from abnormal conditions. This includes separate reset circuits for the MCU Domain to ensure safe recovery in the event of an error in the Main Domain.
Fail-Safe Circuit Design: The system should return to a safe state in case of a fault. Redundant designs can be used so that if one function fails, another can take over to maintain safety.

4. Fault Detection and Monitoring

WATCHDOG Timer: Use WATCHDOG timers for both the Main and MCU Domains to monitor if the software is running correctly. If a fault occurs, the watchdog timer will trigger a reset to recover the system safely.
Fault Injection Testing: Perform fault injection testing to simulate faults and ensure that the system responds correctly to them. This helps validate the functional safety design.

5. Safety in Inter-Domain Communication

ISOLATORS: Use isolators (e.g., optical or digital isolators) for communication between the Main and MCU Domains to prevent electrical interference. This isolation helps maintain functional safety during faults.
Multi-Channel Communication Systems: For higher reliability, use multiple communication channels to transmit critical data. If one channel fails, another can take over, preventing data loss or corruption.

6. Integration of Safety in Hardware and Software

Compliance with Functional Safety Standards: Ensure compliance with functional safety standards such as ISO 26262. This standard provides a framework for the safe design and operation of systems, and both hardware and software must meet its requirements.
Synchronization between Hardware and Software: Ensure the hardware and software work together to maintain functional safety. Software errors should not affect hardware operations, and safety functions should be integrated at both levels.

7. Diagnostic and Logging Capabilities

Diagnostic Circuits: Design diagnostic circuits that can monitor the health of the system in real time. This helps in detecting faults early and understanding the root cause.
Logging and Alerts: Implement logging mechanisms to record critical errors and provide alerts when faults occur. These logs help to troubleshoot issues and improve system reliability.

8. EMI/EMC Protection

Signal Integrity: Carefully design the PCB layout to ensure signal integrity, especially for high-speed signals. Use proper isolation, shielding, and routing techniques to reduce electromagnetic interference (EMI).
Circuit Protection: Design protection circuits to safeguard against high-voltage or high-frequency interference that could affect the system's performance. Filters and snubber circuits can help protect sensitive components.

Conclusion

To implement functional safety with the TI DRA829 SoC, you need to focus on ensuring power and signal integrity, isolating critical systems, and designing fault detection and recovery mechanisms. Each domain (Main Domain and MCU Domain) should be independently designed to ensure that any fault in one domain does not affect the other, and that the system as a whole remains safe even during failures. By following these guidelines, you can build a system that meets functional safety requirements and operates reliably in critical applications.

0 Kallikuppa Sreenivasa 2 months ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 198259 points

Hi Board designers.

Please refer additional collaterals for PDN

AM26x Hardware Design Guidelines

https://www.ti.com/lit/ug/sprabj8d/sprabj8d.pdf

PCB Design Requirements for VDD_MPU_IVA Power
Distribution Network for TI OMAP3630, AM37xx, and
DM37xx Microprocessors
https://www.ti.com/lit/an/sprabj7/sprabj7.pdf

66AK2G1x: EVMK2GX General Purpose EVM Power
Distribution Network Analysis
https://www.ti.com/lit/an/sprace6/sprace6.pdf

How to Measure Impedance of a Power Distribution
Network of a DC-DC Converter
https://www.ti.com/lit/an/sluaai3/sluaai3.pdf

Power Delivery Network Analysis
www.ti.com/.../swpa222a.pdf

66AK2G0x General-Purpose EVM Power Distribution
Network Analysis
www.ti.com/.../sprac38.pdf

TI Designs: TIDEP-0100
AM570x Six-Layer Reference Design
www.ti.com/.../tidue41.pdf

General hardware design/BGA PCB design/BGA
decoupling
www.ti.com/.../sprabv2.pdf

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1405480/dra77p-power-delivery-network-pdn---design-guides

Regards,

Sreenivasa

0 Kallikuppa Sreenivasa 1 month ago in reply to Kallikuppa Sreenivasa

TI__Guru**** 198259 points

Hi Board designers.

Please refer below inputs related to PCB pattern

(32) [FAQ] AM625: PCB Pattern Recommendations for Specific Peripherals - Processors forum - Processors - TI E2E support forums

Is there any recommendations or recommended values (for interconnect length or CLK-to-DATA interconnect difference) for the peripherals below? Is there any documentation that lists this?

①　eMMC、SD card
②　LVDS
③　SPI、QSPI（OSPI）

Yes, these requirements are defined in the respective Timing Conditions table found in the timing sections of the datasheet.

(+) [FAQ] AM625: Disturance on OSPI CLK connected to SPI NOR - Processors forum - Processors - TI E2E support forums

I personally think it is a mistake providing multiple chip select pins on this peripheral. It is misleading and makes someone think they can connect multiple devices, when this implementation is very problematic.

The problem with connecting multiple devices is related to your observation on the clock. You see this distortion on the source end of the signal trace because the output buffer has about the same source impedance as the signal trace. When the signal changes from low to high or high to low, the voltage applied to the signal is divided by the ratio of output buffer source impedance and the signal trace impedance. It is basically a voltage divider that results in a mid-supply voltage being applied to the signal. This mid-supply voltage propagates down the signal trace until it encounters a high-impedance or open-circuit, where the mismatch in impedance results in an in-phase reflection that causes the voltage at the far end to make a continuous transition from VDD to VSS or VSS to VDD. This reflection returns back to the source, where the voltage at the source will not continue to VDD or VSS until this reflection has returned. The length of the mid-supply step function will be equal to two times the propagation time of the clock signal trace. The step function gets shorter as you get closer to the end of the signal trace, but not completely gone until the very end.

A device connected anywhere other than the far end of the signal trace will observe the same step function on the clock signal. Connecting a device clock input anywhere in the middle of a clock signal trace is a very bad design practice because there is a good chance the output of the clock input buffer of this device will generate internal clock glitches when this mid-supply voltage pauses near the switching threshold of the input buffer. You cannot split the signal trace into two paths without creating impedance discontinuities which also causes signal distortion. Inserting buffers will resolve the impedance mismatch issue but inserts delay in the clock path, which may cause a timing violation because the peripheral was timing closed assuming a direct connection without any buffer delays.

Connecting your NOR memory device to the middle of the clock signal was a mistake. You must resolve this issue by disconnecting any signal trace that extends beyond the attached device to prevent any internal clock glitch issues.

Most of the AM62x pins power-up turned off, so you need include external pull resistors to hold any attached device inputs in a valid logic state until the IOs and associated peripheral module has been initialized by software. You should never allow CMOS inputs to float. this is especially true for the AM62x inputs. All AM62x inputs which have been enabled must be held in a valid logic state that is above the VIHSS or VILSS as defined in the respective electrical characteristics section of the datasheet. The AM62x device could be damaged if your design allows any enabled inputs to float to mid-supply voltages for an accumulated period of time over the life of the product.

I am considering suppressing EMI noise caused by SPI_CLK.
Is there any reduction method other than the following?
-Shorten the CLK line.
-Dull CLK by inserting a resistor or a capacitor on the order of pF.
-Lower the impedance of the power supply and signal ground.

All of these option potentially have an effect on interface timing. The best option of the three mentioned is reducing overall length of the clock trace. The worst option is reducing supply impedance, as this will effect all IOs sharing a common IO power rail.

Which SPI are you asking about, McSPI or OSPI?

The maximum operating frequency of McSPI is much lower than OSPI, so there is a much better change for it to have enough timing margin to support a slower clock transition. I would not recommend this for OSPI unless you reduce the operating frequency significantly lower than its maximum operating frequency.

The timing parameters provided in the datasheet are based on the conditions defined at the beginning of each peripheral timing section. You need to ensure your design is compliant to all of these conditions and parameters. We recommend performing a timing analysis of each peripheral using switch characteristics of each device along with actual PCB delays to confirm all timing requirements are met.

Timing closure of each McSPI interfaces was performed with maximum load capacitance of 12pF. So there is a good chance the 100pF load will delay the clock and cause the timing parameter values defined in the datasheet to be invalid. So you will need to characterize McSPI timing with this load and confirm there is still enough margin for the interface.

I will need to ask our IO design team if the 100pF load on SPI_CLK will cause any long-term reliability issues.

We haven’t done IO reliability assessment with loads this large. One potential problem could be degradation due to HCI/CHC when driving larger loads. Therefore, connecting a 100pf capacitor SPI_CLK is not recommended.

There is a Timing Conditions table at the beginning of each peripheral timing section in the datasheet, where the maximum capacitance is defined. Your system should be designed to be compliant to the max capacitance defined in the respective Timing Conditions table.

The max output load capacitive defined in the datasheet is the combination of everything connected to the pin.

Connecting a 100pf capacitor directly to the output buffer causes large peak current to flow through the AM64x power rails and output buffer to the capacitor. This large capacitive load applies more stress to the output buffer than expected and introduces larger than expected ground bounce which introduces noise into the entire AM64x device.

Inserting a series resistor before any discrete capacitor load will reduce the current that flows through the AM64x power rails and output buffer. However, the RC circuit would need to be placed near the AM64x device to be effective in reducing the signal slew rate which is what you are trying to do to reduce EMI.

EMI issues is a typically a system implementation issue and has many variables which influence the profile of radiated emissions. PCB layout issues are the mostly likely contributor. For example, a common contribution to EMI has been seen when customers route signals through board to board connectors or board to cable connectors without low loop inductance return ground paths which can cause signals to radiate noise. Is the SPI_CLK signal routed such that it has a low impedance return reference along the entire path of the signal? For example, does the signal cross any split reference planes or does it transition from one reference plane to another reference plane without a nearby a stitching via or stitching capacitor?

Regards,

Sreenivasa