Hello Justin,

Schematics will beneficial. I've sent a connection request in the E2E.

Meanwhile, can you also confirm MCU_RESETSTATz is also staying low?

Thanks,

Stan

I have sent over the schematic. I have attached a capture of MCU_RESETSTATz on power up. We left the pin floating so looks like some noise

Hi Justin,

The pdf file is non-searchable. It's very hard to review. Can you please generate a searchable format pdf?

Otherwise, from your oscilloscope snapshots, I can see VSYS overshoots > 10% * 3.3V, which is beyond absolute maximum ratings. Even though this might not be the root cause, this is a reliability concern in future.

Regards,

Stan

That's a good point, we will look into this and post an update. I've also sent over a searchable PDF. 

Regarding our two concerns above, would any of them be problems preventing the processor from exiting reset?

Hello Justin, 

Can you please confirm all the processor supplies are available.

Can you probe the WKUP_CLKOUT0 and PORz_OUT pins.

Regards,

Sreenivasa

I've captured new scopes using a different external power supply. I can confirm all processor supplies are available as seen in Run 1:

1. Waveforms A + B: VDD_3V3

2. Waveform C: VDDA_1V8

3. Waveform D: VDD_1V8 + VDD_SD

4. Waveform E: VDD_DDR

5. Waveforms F + G + H: VDD_CORE

6. Waveform I: VPP is pulled down to GND

7. Waveform J: powered by VDD_1V8

8. Waveform K: powered by VDDA_1V8

Run 1

Yellow: VDD_3V3

Light Blue: VDD_1V8

Purple: VDD_DDR

Dark Blue: VDD_CORE

And power averages:

Same trigger but other scope:

Yellow: VDD_3V3

Light Blue: VDD_SD

Purple: VDDA_1V8

Dark Blue: POR_Z

And power averages:

Run 2

Yellow: VDD_3V3

Light Blue: PORz_OUT

Purple: MCU_RESETz

Dark Blue: PORz

Run 3

Yellow: VDD_3V3

Light Blue: WKUP_CLKOUT0

Purple: -

Dark Blue: MCU_RESETSTATz

Run 4

Yellow: VDD_3V3

Light Blue: 25MHz clock in to processor

Purple: -

Dark Blue: -

The exact part number we have mounted on the boards is AM6232ATCGHAALW

sssssss: 35POLOS

YYY: 131

Hello Justin,

Thank you.

Justin Newkirk said:

Run 3

Yellow: VDD_3V3

Light Blue: WKUP_CLKOUT0

Purple: -

Dark Blue: MCU_RESETSTATz

Can you please capture the WKUP_CLKOUT waveform without any reference to other rails and confirm you care able to see a 25M square wave.

Regards,

Sreenivasa

Hello Justin, 

Can you please confirm you are seeing the issue on a specific board or multiple boards.

Regards,

Sreenivasa

Hello Justin, 

Justin Newkirk said:

Run 2

Yellow: VDD_3V3

Light Blue: PORz_OUT

Purple: MCU_RESETz

Dark Blue: PORz

MCU_RESETz is pulled up to VDD_3V3

MCU_RESETz ramps up and then goes low.

Can you confirm if MCU_RESETz is connected to any external circuit that is pulling the input low.

In the schematics, i do not see the MCU_RESETz connect to any additional circuit.

Can you confirm the schematic provided is complete.

Can you please probe RESET_REQz

Regards,

Sreenivasa

Hello Justin, 

The MCU resetz and warm reset (reset_reqz) seems to be controlled by the MCU.

Can you please confirm the signals are high during power cycle.

I done see a series resistor to isolate the signals.

Regards,

Sreenivasa

Attached is a probe of the WKUP_CLKOUT signal (in purple), looks like a 25Mhz square wave:

We have tested two (neither work) of the five boards in this batch. We will post an update testing the others 

Hello Justin,

I see you pressed the resolved button.

Can you please add a couple of sentences on the resolution.

Regards,

Sreenivasa 

Hello Justin,

Thank you for the note.

Appreciated. 

Please update the thread when you make progress.

Regards,

Sreenivasa 

Hello Justin,

Listed below are general guidelines that you may want to refer and make any updates as required.

AM62x
Refer the Errata for the supported features by different silicon revision for choosing the required OPN

Below are some general guidelines that are recommended to be followed during custom board design
General Notes (For customer to review)
1.SOC or processor - means the sitara processor used in the design
2.Attached device - means DDR or flash memory, communication interface, sensors or other external devices interfaced to the processor
3.We reviewed the schematics to the best. Since the implementation and design flow is customer specific, there may be similar updates that customer will have to review and make the updates.
4.Verify all the core, analog and IO supplies for the SOC are connected to the recommended supply voltage levels
5.Verify all the peripheral core, analog and IO supplies for the SOC are connected through ferrite filter
6.Ensure all the pullups connected to the SOC are pulled up to the correct I/O voltage (matches with the IO supply referenced for the specific IO groups)
7.Verify the device selection section of the data sheet based on the requirement to confirm the device selection
8.Verify the pin configuration for the memory interface, communication and IO interfaces using the sysconfig - pinmux tool
9.Verify the mapping of the schematics symbol pin number and name with the pin name and number as per the pin attributes section of the data sheet
10.Any SoC pad that has a trace connected and not being actively driven needs an external parallel pull
11.Verify Device specific Errata for allowed bootmode configuration and erratas affecting the functionality
12.Verify Pin connectivity table of the data sheet for connecting any unused pins or peripherals including supplies
13.Please read through the SOC data sheet pin connectivity requirements and ensure the recommendations are followed
14.When Adjustable DC/DC or LDO are used, verify the resistor divider ration matches the required output voltage
15.Resistor divider tolerance for discrete DC/DC or LDO output supply feedback is 1% for improved output accuracy
16.Note the I2C interface exceptions and pin connectivity requirements
17.Add provision to isolate and probe the OBSCLK for testing
18.Recommendation is to always perform simulations on the custom board
19.The system designer must use the IBIS model of each device connected to a signal and the PCB signal trace extractions in a simulation environment to determine the rise/fall time of any signal being sourced by AM62x or other processors

SK/EVM design reuse
1.The SK schematics included some optional components that are configured as DNI
2.When customers modify the SK/EVM schematics as part of the custom board design, there will be change in the page numbers as well as reference designator numbers
3.The DNI configuration for the reference designators are reset during this design phase
4.The recommendation is to refer the SK/EVM PDF schematics for the DNI components and make the required updates

Notes related to I2C and SPI
1.Open-drain output type I2C interface - a pullup is required irrespective of IO usage or configuration
2.Open-drain output type I2C interface - does not support high speed when the IO supply and the I2C signals are connected to 3.3V
3.Connecting 3.3V to IO supply group and connecting 1.8V supply to IO is not allowed
4.SPIx_CLK a series resistor recommended when used as SPI clock output
SPIx_CLK add a pull down for the clock input near to the attached device clock input pin

Notes on software SDK version

1.In case the project is a new platform, please ensure the latest SDK is used.
2.In case the project is a derived project using older version/revision, the recommendation is to review the changes (release notes) with respect to the version used vs latest. Based on the changes observed, the required discretion (approach) could be followed - Example: updating any of the drivers of interest (Reach out to the TI applications team through E2E)

Common SOC LVCMOS IO interface guidelines (For customers to review and make updates)
1.Most of the SOC IOs are not fail-safe. No external input is recommended to be applied before the processor supply ramps
2.SOC LVCOMOS IOs have slew rate requirements specified, applying a slow ramp input or connecting a cap at the input is not recommended
3.Connecting a cap load >22pF at the LVCMOS IO output is not recommended. DNI cap or perform simulations based on the use case.
4.SOC IO buffers are off during Reset. A pull is required near to the attached device being driven by the SOC IO that could float
5.Any SOC IO that has a trace connected needs a parallel pull. When adding pull is not feasible, ensure the traces are routed away from noisy signals
6.Connecting processor IOs that can be configured for alternate function, directly to supply or ground is not allowed or recommended (including boot mode inputs). Custom board can have an configuration issue with the firmware and mis-configures these LVCMOS GPIOs that were intended to be inputs, to be outputs driven logic high instead.
7.Verify cap loading of the SOC output (when any cap value >22 pF (use case dependent, max value) is connected, recommendation is to simulate), slew rate of the input signal (LVCMOS input slew should be 1000 ns or less), IO compatibility and fail-safe operation between the SOC IOs and attached devices
8.Ensure ST_EN bit in the PADconfig register is enabled for all the IOs

Regards,

Sreenivasa