SYS/BIOS, OMAP-L138 experimenter kit, is PSC1 memory protected, ARM data abort exception

Damian Gowor

Other Parts Discussed in Thread: SYSBIOS

Hello,

I have just discovered strange situation. I am writing some software for UART peripheral. I am using some code from BSL for configuring UART. Before using UART I must to configure the PSC peripheral using following code:

while (CHKBIT(PSCRegister->PTSTAT, (unsigned int)PowerDomain)) {}

if (CHKBIT(PSCRegister->MDSTAT[(unsigned int)ModuleNo], PSCStateMask) == (unsigned int)NextState)
 return OMAPL138PSCDriver::ErrorAlreadyInRequestedState;

CLRBIT(PSCRegister->MDCTL[(unsigned int)ModuleNo], PSCNextStateMask);
SETBIT(PSCRegister->MDCTL[(unsigned int)ModuleNo], (unsigned int)NextState);
SETBIT(PSCRegister->PTCMD, (unsigned int)PowerDomain);
while (CHKBIT(PSCRegister->PTSTAT, (unsigned int)PowerDomain)) {}

while (CHKBIT(PSCRegister->MDSTAT[(unsigned int)ModuleNo], PSCStateMask) != (unsigned int)NextState) {}

return OMAPL138PSCDriver::NoError;

Well, if I am configuring PSC0 for UART0 everything is OK and works like it should work. When I am trying to configure the PSC1 peripheral for using UART2 the emulator

shows me that ARM raised data abort exception. Here is the LOG from console:

[ARM9_0] in handle: 0x0.
Main stack base: 0xc300c134.
Main stack size: 0x2000.
R0 = 0x00000001 R8 = 0xffffffff
R1 = 0x00000001 R9 = 0xffffffff
R2 = 0x0000000d R10 = 0xffffffff
R3 = 0x00000003 R11 = 0xffffffff
R4 = 0xfffd5160 R12 = 0x01e27000
R5 = 0xc300fa48 [ARM9_0] SP(R13) = 0xc300dff0
R6 = 0x2000005f LR(R14) = 0xc3004a40
R7 = 0xffffffff PC(R15) = 0xc3004b64
PSR = 0x600000df
ti.sysbios.family.arm.exc.Exception: line 174: E_dataAbort: pc = 0xc3004b64, lr = 0xc3004a[ARM9_0] 40.
xdc.runtime.Error.raise: terminating execution

And under the 0x3004b64 we will find following code:

while (CHKBIT(PSCRegister->PTSTAT, (unsigned int)PowerDomain)) {}
 $C$DW$L$_ZN17OMAPL138PSCDriver10PSCTransitEP16PSCRegistersTypeN12PowerDomains16PowerDomainsTypeEN20PSCControlledModules24PSCControlledModulesTypeEN15PSCModuleStates19PSCModuleStatesTypeE$2$B, $C$L17:
c3004b5c: E59DC000 LDR R12, [R13]
c3004b60: E5DD0004 LDRB R0, [R13, #0x4]
c3004b64: E59CC128 LDR R12, [R12, #0x128]
c3004b68: E110000C TST R0, R12
c3004b6c: 1AFFFFFA BNE $C$L17

My question is why the memory area under address 0x01e27000 + 0x128 (PSC1 PTSTAT) is inaccessible?

over 13 years ago

0 Damian Gowor over 13 years ago

Expert 1110 points

I have disabled the cache adding

 var Cache = xdc.useModule('ti.sysbios.hal.Cache');
 Cache.CacheProxy = xdc.useModule('ti.sysbios.hal.CacheNull');

to the configuration file and it works. I have found this information in another post but I would like to know

is there any possibility for not disabling cache and having access to all peripheral memory?

0 ScottG over 13 years ago in reply to Damian Gowor

TI__Mastermind 26780 points

Damian,

Which other post are you referring to that led you to disable the Cache?

Have you seen this post about setting up the MMU to be able to access PSC1?: http://e2e.ti.com/support/embedded/bios/f/355/t/150298.aspx#543633

I think that you should be able to keep Cache enabled, but just need to set up the MMU properly…

Scott

0 Damian Gowor over 13 years ago in reply to ScottG

Expert 1110 points

Hello Scott,

I have found those information in this post:

http://e2e.ti.com/support/embedded/bios/f/355/t/142596.aspx#516937

I am sorry but I can't open this post that you have passed the link to it. It says "Group Not Found".

I must to admit that I have never been configuring MMU and I will do it if there will be no other way.

I am just looking for the simplest way and I was thinking that it can be resolved in some simple

way in SYS/BIOS configuration. Do I must to use ti.sysbios.family.arm.arm9.mmu module to do it?

0 ScottG over 13 years ago in reply to Damian Gowor

TI__Mastermind 26780 points

Damian,

OK, thanks for the link.

I don’t know why the link cannot be clicked on directly. If I try I get the same group not found message. If I cut and paste directly to a browser it is OK. Can you try again: http://e2e.ti.com/support/embedded/bios/f/355/t/150298.aspx#543633

The other post is similar, but there is a short description of how to setup the MMU table entries for access to additional peripherals.

I think the two options are: disable both MMU and Cache (with loss of MMU features and performance), or setup MMU table entries for the addresses you need to access.

Scott

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SYS/BIOS, OMAP-L138 experimenter kit, is PSC1 memory protected, ARM data abort exception