AM62P: Multiple DDR Settings

Marinus, i would recommend a different approach, which would be to come up with a common configuration that would work with each DDR alternative.  Most DDR memories comply to a JEDEC spec, which means that most timing parameters are exactly the same, or very close, to the point where you are likely to be able to come up with a configuration that works across multiple vendors.  As long as you are selecting devices with similar densities and topologies, you should be able to accomplish this.  Also, this approach would be much less complicated then trying to maintain different configuration in an EEPROM or dynamically changing configurations.

Regards,

james

Hi James,

thank you for the tip, of course it may work fine when selecting a very similar chip.

But apart from this we are wondering whether this dynamic configuration change is possible, because this would allow us to use different topology chips as a replacement. So we would appreciate if you could show us a possible way how to implement this feature, or please notify us if this is not possible with AM62P.

Best regards,

Gábor

Can you explain what kind of alternatives they are thinking of that would be possible with one design?  You still might be able to use a common config.

In fact, i just answered a similar question here:   AM62D-Q1: LPDDR4 Device Density vs. DDRSS Configuration 

I think depending on the the variations of dynamic configurations they want to support, they still might be able to come up with a common config.

A dynamic config at a high level would just add a few steps before the beginning of the DDR initialization.  It would entail decoding EEPROM or pin strapping prior to loading the DDR driver and pointing to the appropriate config data structure.  That data structure would be used by the driver to load all DDR controller/PHY registers to kick off the initialization and training.

Regards

James

Of course I can explain it. Currently a dual channel dual rank memory is used in the prototype, but due to RAM supplier shortages we are thinking about also single rank alternatives, which has less chip select and clock enable lines. I suppose that this difference in memory chip architecture surely need some change in software configuration, too.

So I should go back to the original topic: can we read GPIOs and/or I2C in early boot stages? Software colleague informed me with more details: the question is regarding to U-Boot SPL (Secondary Program Load) phase, which is started directly after ROM boot stage.

Thank you in advance,

Gábor

Ok, yes, the single/dual rank devices would need different software configurations.  

I believe GPIOs or i2c can be used in early boot stages.  I will have to pass this to our software experts to help guide this.

Regards,

James

Thank you if you could invoke software experts for this question.

Our software colleagues figured out that WKUP and/or MCU domain peripherals might be used if any, but WKUP does not have GPIO, only I2C, the usability of MCU domain GPIOs is a question. And it is also a question how to configure them in U-Boot. We are looking forward to the help of your experts, thank you.

Best regards,

Gábor