DRA821U: DRA821 SPI Digital Timing Question

Hi Jonathan,

Jonathan West said:

Do SM8 & SM7 still apply when manually asserting chip select? If yes, does that imply that the word to transmit has to be loaded prior to asserting chipselect?

When manually asserting CS in software, the respective datasheet timings will no longer apply.

Jonathan West said:

For our application with 2 32-bit cycles with CS continuously asserted across both cycles, what's the setup and hold time of SPI_D(x)(OUT) relative to SPI_SCLK(OUT) as there is no falling edge of chip select for the 2nd 32bit bus operation?SPI Timing Question for TI.pptx  Is the first bit asserted [SM8-SM7]ns before the first clock edge?

I'm unsure about when the controller launches the first data bit during the 2nd 32-bit operation. Please allow a couple days to look into this.

Regards,
Mark

Given SM8 and SM7 don't apply to the first transaction either, please confirm setup/hold time for both 32cycle bus transactions. Thanks!

Hi Jonathan,

The second word is launched after the data is put into the transmit shift register from the FIFO. The time this takes would satisfy the SM6 timing.

Please let me know if that clarifies your ask.

Regards,
Mark

Here's an updated diagram to clarify my questions:

[A] Min/Max Timing from setting/clearing force bit to CS output toggling

[B] Min/Max timing from writing data into TX FIFO to first clock edge

[C][D] Relative timing of DRA821 data output relative to the 1st edge of the clock

Hi Jonathan,

Regarding [A] and [B]: these timings are not available. Are you encountering any specific issues with these?

Regarding [C] and [D]: can you calculate the setup and hold timing on the following bit at your configured clock speed? The calculated timing would be representative of the timing on the first launched bit. Another option is to configure PHA=1, where all launched bits follows the datasheet's SM6 timing.

Regards,
Mark

Hi Mark,

Ok to skip [A] and [B]. Is [D] 1/2 clock period + SM6 (+/-2)? We need to know when the first bit is valid on the bus [C]. We can't change PHA to 1 as the device on the far end of the bus is using rising clock edge to latch MOSI.

Jonathan,

Setup and hold time will be approximately equal to SM2/SM3 - 2ns (SM6) when launching on one edge and capturing on the opposite edge (falling then rising, in this case). For example, a 20.8ns cycle time would mean we have 7.4ns of setup and hold time.

Formula: (0.5*SPI_CLK - 1ns) - 2ns

Please let me know if this clears things up.

Regards,
Mark

To confirm: When manually controlling chip select via software and POL=0.

Assertion of SPI clock and data out is independent of chip select and instead is driven some (UNKNOWN?) amount of time after a transmit word is written to the transmit fifo?

processor asserts clock rising edge and 1st data bit at the same time. data bit will leave the chip SM6 relative to 1st rising clock edge leaving chip?

Thinking about this more - this doesn't explain how the first bit comes out. What is the relative timing of the first bit being driven on MOSI relative to the first rising edge of CLK? If driven at the same time, then the 1st bit would only be present on the bus for 1/2 a clock cycle. 

Is it this (t = clock cycle)? 

t0: bit0 sent

t0.5: 1st clk rising edge

t1: bit 1 sent, 1st clk falling edge

Or this?

t0: 1st clk rising edge, bit0 sent

t0.5: 1st clk falling edge, bit1 sent

Something else?

Hi Jonathan,

Based on my bench measurement, the first databit of a word launches on the first active CLK edge (falling edge in this case) - P (SPI_CLK period in ns).

Regards,
Mark

Like this?

Sorry, small correction. The timing for the databit will be SM6 - P.

Regards,
Mark

Thanks for catching that - does this look correct? Changed first bit to start 1 clock cycle before Bit2 which includes uncertainty for SM6 timing parameter.