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Original question:

AM620-Q1: AM62xx Watchdog resets despite keepalive (ioctl/write/echo)

AM62L-LINUX-RT-SDK: WDT cannot be cleared from Linux's userland

TO
Prodigy 170 points

Part Number: AM62L-LINUX-RT-SDK
Other Parts Discussed in Thread: AM62L

Hi Support,

We are experiencing an issue with the watchdog timer on the AM62Lx platform, similar to what is described in the following forum thread: 

https://e2e.ti.com/support/tools/simulation-hardware-system-design-tools-group/sim-hw-system-design/f/simulation-hardware-system-design-tools-forum/1604070/am620-q1-am62xx-watchdog-resets-despite-keepalive-ioctl-write-echo/6181130?tisearch=e2e-sitesearch&keymatch=rti_wdt.c#

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1338070/am625-how-to-control-the-watchdog

Issue

I enabled WDT with reference to the following.
https://software-dl.ti.com/processor-sdk-linux-rt/esd/AM62LX/11_02_08_02/exports/docs/linux/Foundational_Components/Kernel/Kernel_Drivers/Watchdog.html

I ran the WDT sample C code using the following as a reference.
However, it will reset after about 60 seconds.

image.png
Question

In the AM62L platform, it seems to have been resolved in the thread above, but has the issue not been resolved for the AM62L platform?

The operating environment is as follows
 SDK: AM62L-LINUX-RT-SDK
 Version: 11.02.08.02
 Board: Custom Board

Regards,
TO

  • 0
    Prodigy 170 points

    Sorry, that was a typo.


    Question

    In the AM62xx platform, it seems to have been resolved in the thread above, but has the issue not been resolved for the AM62L platform?

  • 0 in reply to TO
    TI__Guru** 108210 points

    Hello TO,

    Does this patch fix the behavior?
    AM62L: Watchdog not working

    I am checking with the developers to see if it was intentional that this patch did not make its way into SDK 11.2, or if this was a miss.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 170 points

    Hello Nick,

    Thank you for your support.

    When I checked the kernel driver, it appears that SDK 11.2 has already had the patch applied.

    https://github.com/TexasInstruments/ti-linux-kernel/commit/e7da049e7202df63a88af996af8288590ff50d68

    Regards,
    TO

  • 0 in reply to TO
    Prodigy 170 points

    Hello Nick,

    I may have found the cause.

    On my custom board, an external crystal is not mounted on LFOSC0.

    And checking the CPU register settings showed the following:

    MAIN_CTRL_MMR_CFG2_WWD0_CLKSEL(0x0911D000) is 0x00000001. 
    so, DEVICE_CLKOUT_32K has been selected.

      

    WKUP_CTRL_MMR_CFG2_CLK_32K_RC_CLKSEL(0x43020100) is 0x00000003.
    so, LFOSC0_CLKOUT has been selected.  However, LFOSC0 is not mounted on my custom board.

    Question

    How can I change the WKUP_CTRL_MMR_CFG2_CLK_32K_RC_CLKSEL register to 0x00000002 in a Linux device tree?

    I changed the WKUP_CTRL_MMR_CFG2_CLK_32K_RC_CLKSEL with devmem2, and it operates without issues.

    Regards,

    TO

  • 0 in reply to TO
    TI__Guru** 108210 points

    Hello TO,

    Good catch on finding that patch for AM62L watchdog support.

    FYI: RC clock might not be a very stable clock source 

    I remember someone on our hardware team telling me that the internal RC clock could have pretty variable frequencies. I am double-checking with that person now. But if true, I would advise against using an internal RC clock for the watchdog counter, since it could potentially drift relative to the system time assuming that the system time is being driven by a separate oscillator.

    How to change the clock source 

    This is the magic code in the AM62L devicetree file which sets the clock source for main_rti0 and main_rti1:

    k3-am62l-main.dtsi

        main_rti0: watchdog@e000000 {
                compatible = "ti,am62l-rti-wdt";
                reg = <0x00 0x0e000000 0x00 0x100>;
                clocks = <&scmi_clk 277>;
                power-domains = <&scmi_pds 60>;
                assigned-clocks = <&scmi_clk 277>;
                assigned-clock-parents = <&scmi_clk 274>;
        };

        main_rti1: watchdog@e010000 {
                compatible = "ti,am62l-rti-wdt";
                reg = <0x00 0x0e010000 0x00 0x100>;
                clocks = <&scmi_clk 283>;
                power-domains = <&scmi_pds 61>;
                assigned-clocks = <&scmi_clk 283>;
                assigned-clock-parents = <&scmi_clk 280>;
        };

    What I would normally have you do is look up the clock IDs in the TISCI documentation, and switch the assigned-clock-parents and assigned-clocks as needed. However, it does not look like the clock IDs have been published in the TISCI docs as of SDK 11.2:
    https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/index.html#am62lx

    Where this is what I would expect the page to look like:
    https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/am62x/clocks.html 

    I am following up with a team member to see where I can get that information for you. Please ping the thread if I have not responded by Friday.

    Regards,

    Nick

  • 0 in reply to Nick Saulnier
    Prodigy 170 points

    Hello Nick,

    Thank you for the information.

    On the AM62 platform I can change the clock source as follows.

    main_rti0: watchdog@e000000 {
	compatible = "ti,j7-rti-wdt";
	reg = <0x00 0x0e000000 0x00 0x100>;
	clocks = <&k3_clks 125 0>;
	power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
	assigned-clocks = <&k3_clks 125 0>;
	assigned-clock-parents = <&k3_clks 125 2>;
};

    I expect that on the AM62L platform it will also be possible to change the clock source via the device tree.

    I look forward to hearing from you.

    Regards,
    TO

  • +1 in reply to TO
    TI__Guru** 108210 points

    Hello TO,

    RC clock discussion, continued 

    From my discussion with the HW engineer:

    Nick: you told me that RC clock sources within the processor could have frequency variations as much as +/- 50%, right? Do you know if that was just random frequency swings, or are the impacts on frequency more from PVT variations?

    HW engineer: Mostly PVT.  In reality, 50% is probably way exaggerated for most silicon

    So the changes in RC clock frequency due to PVT are not as big as I was concerned about, but there is still an unknown impact. The internal RC clock might be fine for development and debug, but I would still not use an RC clock for my own design, in order to avoid unexpected edge cases (for example, if the product started resetting due to watchdog when the product gets too cold and the RC clock frequency drifted more than 2% away from the Linux system time).

    Setting the WDT clock source

    Ahh, this was the issue. AM62L uses the SCMI protocol instead of the TISCI protocol. Looks like the clock IDs are documented in the TF-A project:
    https://software-dl.ti.com/processor-sdk-linux/esd/AM62LX/latest/exports/docs/linux/Foundational_Components_ATF.html

    From
    https://github.com/TexasInstruments/arm-trusted-firmware/blob/ti-master/docs/plat/ti-am62l.rst 

    +--------+--------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+-------------+
| PARENT | AM62LX_DEV_RTI0                            | AM62LX_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_HFOSC0_CLK                                                                   | RTI0                       | 273         |
+--------+--------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+-------------+
| PARENT | AM62LX_DEV_RTI0                            | AM62LX_DEV_RTI0_RTI_CLK_PARENT_CLK_32K_RC_SEL_OUT0                                                                    | RTI0                       | 274         |
+--------+--------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+-------------+
| PARENT | AM62LX_DEV_RTI0                            | AM62LX_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLKOUT                                                                 | RTI0                       | 275         |
+--------+--------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+-------------+
| PARENT | AM62LX_DEV_RTI0                            | AM62LX_DEV_RTI0_RTI_CLK_PARENT_GLUELOGIC_RCOSC_CLK_1P0V_97P65K3                                                       | RTI0                       | 276         |
+--------+--------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+-------------+
| MUX    | AM62LX_DEV_RTI0                            | AM62LX_DEV_RTI0_RTI_CLK                                                                                               | RTI0                       | 277         |
+--------+--------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+-------------+
| PARENT | AM62LX_DEV_RTI0                            | AM62LX_DEV_RTI0_VBUSP_CLK                                                                                             | RTI0                       | 278         |
+--------+--------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------+-------------+

    Regards,

    Nick