TDA4VEN-Q1: Custom memory mapping for Linux + RTOS

Stuart Burtner

Part Number: TDA4VEN-Q1

Hi,

We have a tda4ven chip down design with the same memory part, but with 4GB instead of 8GB.

We have updated the memory timings, but when I go to change the memory size & reservations in linux & RTOS, the system crashses shortly after trying to run any vision application.

I have been following this guide here: https://software-dl.ti.com/jacinto7/esd/processor-sdk-rtos-j722s/10_00_00_05/exports/docs/psdk_rtos/docs/user_guide/developer_notes_memory_map.html

What else am I missing to make this work?

See system memory map html below:

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    <head>
        <title>System Memory Map for Linux+RTOS mode</title>
    </head>
    <body>
        <h1>System Memory Map for Linux+RTOS mode</h1>
        <p>Note, this file is auto generated using PyTI_PSDK_RTOS tool</p>
        <table class="tg">
            <tr>
                <th class="tg-fjir">Name</th>
                <th class="tg-fjir">Start Addr</th>
                <th class="tg-fjir">End Addr</th>
                <th class="tg-fjir">Size </th>
                <th class="tg-fjir">Attributes</th>
                <th class="tg-fjir">Description</th>
            </tr>
            <tr>
                <td class="tg-kftd">L2RAM_C7x_1_MAIN</td>
                <td class="tg-kftd">0x7E000000</td>
                <td class="tg-kftd">0x7E1FFFFF</td>
                <td class="tg-kftd"> 2.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">L3 for C7x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">L2RAM_C7x_2_MAIN</td>
                <td class="tg-6sgx">0x7E200000</td>
                <td class="tg-6sgx">0x7E3FFFFF</td>
                <td class="tg-6sgx"> 2.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">L3 for C7x_2</td>
            </tr>
            <tr>
                <td class="tg-kftd">L2RAM_C7x_1_AUX</td>
                <td class="tg-kftd">0x7F000000</td>
                <td class="tg-kftd">0x7F03BFFF</td>
                <td class="tg-kftd">240.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">L2 for C7x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">L2RAM_C7x_1_AUX_AS_L1</td>
                <td class="tg-6sgx">0x7F03C000</td>
                <td class="tg-6sgx">0x7F03FFFF</td>
                <td class="tg-6sgx">16.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">L1 for C7x_1</td>
            </tr>
            <tr>
                <td class="tg-kftd">L2RAM_C7x_2_AUX</td>
                <td class="tg-kftd">0x7F800000</td>
                <td class="tg-kftd">0x7F83BFFF</td>
                <td class="tg-kftd">240.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">L2 for C7x_2</td>
            </tr>
            <tr>
                <td class="tg-6sgx">L2RAM_C7x_2_AUX_AS_L1</td>
                <td class="tg-6sgx">0x7F83C000</td>
                <td class="tg-6sgx">0x7F83FFFF</td>
                <td class="tg-6sgx">16.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">L1 for C7x_2</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU1_0_IPC</td>
                <td class="tg-kftd">0xA1000000</td>
                <td class="tg-kftd">0xA10FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU1_0 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU1_0_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xA1100000</td>
                <td class="tg-6sgx">0xA11003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU1_0 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU1_0_IPC_TRACE</td>
                <td class="tg-kftd">0xA1100400</td>
                <td class="tg-kftd">0xA11FFFFF</td>
                <td class="tg-kftd">1023.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU1_0 for Linux IPC trace</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU1_0</td>
                <td class="tg-6sgx">0xA1200000</td>
                <td class="tg-6sgx">0xA1FFFFFF</td>
                <td class="tg-6sgx">14.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU1_0 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU2_0_IPC</td>
                <td class="tg-kftd">0xA2000000</td>
                <td class="tg-kftd">0xA20FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU2_0 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU2_0_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xA2100000</td>
                <td class="tg-6sgx">0xA21003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU2_0 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU2_0_IPC_TRACE</td>
                <td class="tg-kftd">0xA2100400</td>
                <td class="tg-kftd">0xA21FFFFF</td>
                <td class="tg-kftd">1023.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU2_0 for Linux IPC trace</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU2_0</td>
                <td class="tg-6sgx">0xA2200000</td>
                <td class="tg-6sgx">0xA3FFFFFF</td>
                <td class="tg-6sgx">30.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU2_0 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">IPC_VRING_MEM</td>
                <td class="tg-kftd">0xA5000000</td>
                <td class="tg-kftd">0xA6FFFFFF</td>
                <td class="tg-kftd">32.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">Memory for IPC Vring's. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-6sgx">APP_LOG_MEM</td>
                <td class="tg-6sgx">0xA7000000</td>
                <td class="tg-6sgx">0xA703FFFF</td>
                <td class="tg-6sgx">256.00 KB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">Memory for remote core logging</td>
            </tr>
            <tr>
                <td class="tg-kftd">TIOVX_OBJ_DESC_MEM</td>
                <td class="tg-kftd">0xA7040000</td>
                <td class="tg-kftd">0xAAFFFFFF</td>
                <td class="tg-kftd">63.75 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">Memory for TI OpenVX shared memory. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-6sgx">APP_FILEIO_MEM</td>
                <td class="tg-6sgx">0xAB000000</td>
                <td class="tg-6sgx">0xAB3FFFFF</td>
                <td class="tg-6sgx"> 4.00 MB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">Memory for remote core file operations</td>
            </tr>
            <tr>
                <td class="tg-kftd">TIOVX_LOG_RT_MEM</td>
                <td class="tg-kftd">0xAB400000</td>
                <td class="tg-kftd">0xACFFFFFF</td>
                <td class="tg-kftd">28.00 MB</td>
                <td class="tg-kftd"></td>
                <td class="tg-kftd">Memory for TI OpenVX shared memory for Run-time logging. MUST be non-cached or cache-coherent</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_1_IPC</td>
                <td class="tg-6sgx">0xAD000000</td>
                <td class="tg-6sgx">0xAD0FFFFF</td>
                <td class="tg-6sgx">1024.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_1 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_1_RESOURCE_TABLE</td>
                <td class="tg-kftd">0xAD100000</td>
                <td class="tg-kftd">0xAD1003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_1 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_1_IPC_TRACE</td>
                <td class="tg-6sgx">0xAD100400</td>
                <td class="tg-6sgx">0xAD1FFFFF</td>
                <td class="tg-6sgx">1023.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_1 for Linux IPC trace</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_1_BOOT</td>
                <td class="tg-kftd">0xAD200000</td>
                <td class="tg-kftd">0xAD2003FF</td>
                <td class="tg-kftd">1024 B</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_1 for boot section</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_1_VECS</td>
                <td class="tg-6sgx">0xAD400000</td>
                <td class="tg-6sgx">0xAD403FFF</td>
                <td class="tg-6sgx">16.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_1 for vecs section</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_1_SECURE_VECS</td>
                <td class="tg-kftd">0xAD600000</td>
                <td class="tg-kftd">0xAD603FFF</td>
                <td class="tg-kftd">16.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_1 for secure vecs section</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_1</td>
                <td class="tg-6sgx">0xAD604000</td>
                <td class="tg-6sgx">0xB0FFFFFF</td>
                <td class="tg-6sgx">57.98 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_1 for code/data</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_2_IPC</td>
                <td class="tg-kftd">0xB1000000</td>
                <td class="tg-kftd">0xB10FFFFF</td>
                <td class="tg-kftd">1024.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_2 for Linux IPC</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_2_RESOURCE_TABLE</td>
                <td class="tg-6sgx">0xB1100000</td>
                <td class="tg-6sgx">0xB11003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_2 for Linux resource table</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_2_IPC_TRACE</td>
                <td class="tg-kftd">0xB1100400</td>
                <td class="tg-kftd">0xB11FFFFF</td>
                <td class="tg-kftd">1023.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_2 for Linux IPC trace</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_2_BOOT</td>
                <td class="tg-6sgx">0xB1200000</td>
                <td class="tg-6sgx">0xB12003FF</td>
                <td class="tg-6sgx">1024 B</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_2 for boot section</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_2_VECS</td>
                <td class="tg-kftd">0xB1400000</td>
                <td class="tg-kftd">0xB1403FFF</td>
                <td class="tg-kftd">16.00 KB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_2 for vecs section</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7x_2_SECURE_VECS</td>
                <td class="tg-6sgx">0xB1600000</td>
                <td class="tg-6sgx">0xB1603FFF</td>
                <td class="tg-6sgx">16.00 KB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for C7x_2 for secure vecs section</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7x_2</td>
                <td class="tg-kftd">0xB1604000</td>
                <td class="tg-kftd">0xB4FFFFFF</td>
                <td class="tg-kftd">57.98 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for C7x_2 for code/data</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_MCU1_0_LOCAL_HEAP</td>
                <td class="tg-6sgx">0xB5000000</td>
                <td class="tg-6sgx">0xB57FFFFF</td>
                <td class="tg-6sgx"> 8.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for MCU1_0 for local heap</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_MCU2_0_LOCAL_HEAP</td>
                <td class="tg-kftd">0xB5800000</td>
                <td class="tg-kftd">0xB77FFFFF</td>
                <td class="tg-kftd">32.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for MCU2_0 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_SHARED_MEM</td>
                <td class="tg-6sgx">0xC0000000</td>
                <td class="tg-6sgx">0xDFFFFFFF</td>
                <td class="tg-6sgx">512.00 MB</td>
                <td class="tg-6sgx"></td>
                <td class="tg-6sgx">Memory for shared memory buffers in DDR</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE</td>
                <td class="tg-kftd">0x100000000</td>
                <td class="tg-kftd">0x103FFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for c7x_1 for non cacheable local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_1_LOCAL_HEAP_NON_CACHEABLE</td>
                <td class="tg-6sgx">0x100000000</td>
                <td class="tg-6sgx">0x103FFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_1 for local heap wrt c7x_2</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_SCRATCH_NON_CACHEABLE</td>
                <td class="tg-kftd">0x104000000</td>
                <td class="tg-kftd">0x107FFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for c7x_1 for non cacheable scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_1_SCRATCH_NON_CACHEABLE</td>
                <td class="tg-6sgx">0x104000000</td>
                <td class="tg-6sgx">0x107FFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Virtual address of non-cacheable DDR for c7x_1 for Scratch Memory wrt c7x_2</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP</td>
                <td class="tg-kftd">0x108000000</td>
                <td class="tg-kftd">0x10BFFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for c7x_1 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_1_LOCAL_HEAP</td>
                <td class="tg-6sgx">0x108000000</td>
                <td class="tg-6sgx">0x10BFFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_1 for local heap wrt c7x_2</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_SCRATCH</td>
                <td class="tg-kftd">0x10C000000</td>
                <td class="tg-kftd">0x10FFFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">DDR for c7x_1 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_1_SCRATCH</td>
                <td class="tg-6sgx">0x10C000000</td>
                <td class="tg-6sgx">0x10FFFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Virtual address of cacheable DDR for c7x_1 for Scratch Memory wrt c7x_2</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_2_LOCAL_HEAP_NON_CACHEABLE</td>
                <td class="tg-kftd">0x110000000</td>
                <td class="tg-kftd">0x113FFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_2 for local heap wrt c7x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE</td>
                <td class="tg-6sgx">0x110000000</td>
                <td class="tg-6sgx">0x113FFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for c7x_2 for non cacheable local heap</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_2_SCRATCH_NON_CACHEABLE</td>
                <td class="tg-kftd">0x114000000</td>
                <td class="tg-kftd">0x117FFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Virtual address of non-cacheable DDR for c7x_2 for Scratch Memory wrt c7x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_SCRATCH_NON_CACHEABLE</td>
                <td class="tg-6sgx">0x114000000</td>
                <td class="tg-6sgx">0x117FFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for c7x_2 for non cacheable scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_2_LOCAL_HEAP</td>
                <td class="tg-kftd">0x118000000</td>
                <td class="tg-kftd">0x11BFFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Virtual address of cacheable DDR for c7x_2 for local heap wrt c7x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_LOCAL_HEAP</td>
                <td class="tg-6sgx">0x118000000</td>
                <td class="tg-6sgx">0x11BFFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for c7x_2 for local heap</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_2_SCRATCH</td>
                <td class="tg-kftd">0x11C000000</td>
                <td class="tg-kftd">0x11FFFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Virtual address of cacheable DDR for c7x_2 for Scratch Memory wrt c7x_1</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_SCRATCH</td>
                <td class="tg-6sgx">0x11C000000</td>
                <td class="tg-6sgx">0x11FFFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">DDR for c7x_2 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP_NON_CACHEABLE_PHYS</td>
                <td class="tg-kftd">0x880000000</td>
                <td class="tg-kftd">0x883FFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Physical address of non-cacheable DDR for c7x_1 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_1_SCRATCH_NON_CACHEABLE_PHYS</td>
                <td class="tg-6sgx">0x884000000</td>
                <td class="tg-6sgx">0x887FFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Physical address of non-cacheable DDR for c7x_1 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_1_LOCAL_HEAP_PHYS</td>
                <td class="tg-kftd">0x888000000</td>
                <td class="tg-kftd">0x88BFFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Physical address of cacheable DDR for c7x_1 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_1_SCRATCH_PHYS</td>
                <td class="tg-6sgx">0x88C000000</td>
                <td class="tg-6sgx">0x88FFFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Physical address of cacheable DDR for c7x_1 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_2_LOCAL_HEAP_NON_CACHEABLE_PHYS</td>
                <td class="tg-kftd">0x890000000</td>
                <td class="tg-kftd">0x893FFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Non-cacheable DDR for c7x_2 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_SCRATCH_NON_CACHEABLE_PHYS</td>
                <td class="tg-6sgx">0x894000000</td>
                <td class="tg-6sgx">0x897FFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Physical address of Non-cacheable DDR for c7x_2 for Scratch Memory</td>
            </tr>
            <tr>
                <td class="tg-kftd">DDR_C7X_2_LOCAL_HEAP_PHYS</td>
                <td class="tg-kftd">0x898000000</td>
                <td class="tg-kftd">0x89BFFFFFF</td>
                <td class="tg-kftd">64.00 MB</td>
                <td class="tg-kftd">RWIX</td>
                <td class="tg-kftd">Physical address of Cacheable DDR for c7x_2 for local heap</td>
            </tr>
            <tr>
                <td class="tg-6sgx">DDR_C7X_2_SCRATCH_PHYS</td>
                <td class="tg-6sgx">0x89C000000</td>
                <td class="tg-6sgx">0x89FFFFFFF</td>
                <td class="tg-6sgx">64.00 MB</td>
                <td class="tg-6sgx">RWIX</td>
                <td class="tg-6sgx">Physical address of cacheable DDR for c7x_2 for Scratch Memory</td>
            </tr>
        </table>
    </body>
</html>

16 days ago

0 Jared McArthur 16 days ago

TI__Mastermind 24590 points

Hi Stuart Burtner,

Can you share the error logs?

Best,
Jared

0 Stuart Burtner 15 days ago in reply to Jared McArthur

Intellectual 321 points

Jared,

The failure mode depends on how I have my machine configured. Right now I am using this device tree (in uboot and linux):

// SPDX-License-Identifier: GPL-2.0
/*
 * Vision-apps: device-tree overlay
 *
 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
 */

#include <dt-bindings/soc/ti,sci_pm_domain.h>

/dts-v1/;
/plugin/;

&wkup_r5fss0_core0_memory_region {
	status = "disabled";
};

&wkup_r5fss0_core0_dma_memory_region {
	status = "disabled";
};

&mcu_r5fss0_core0_memory_region {
	status = "disabled";
};

&mcu_r5fss0_core0_dma_memory_region {
	status = "disabled";
};

&main_r5fss0_core0_dma_memory_region {
	status = "disabled";
};

&main_r5fss0_core0_memory_region {
	status = "disabled";
};

&c7x_0_dma_memory_region {
	status = "disabled";
};

&c7x_0_memory_region {
	status = "disabled";
};

&c7x_1_dma_memory_region {
	status = "disabled";
};

&c7x_1_memory_region {
	status = "disabled";
};

&rtos_ipc_memory_region {
	status = "disabled";
};

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;

	vision_apps_wkup_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a0000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa0000000 0x00 0x00100000>;
		no-map;
	};
	vision_apps_wkup_r5fss0_core0_memory_region: vision-apps-r5f-memory@a0100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa0100000 0x00 0x00f00000>;
		no-map;
	};
	vision_apps_mcu_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a1000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1000000 0x00 0x00100000>;
		no-map;
	};
	vision_apps_mcu_r5fss0_core0_memory_region: vision-apps-r5f-memory@a1100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa1100000 0x00 0x00f00000>;
		no-map;
	};
	vision_apps_main_r5fss0_core0_dma_memory_region: vision-apps-r5f-dma-memory@a2000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2000000 0x00 0x00100000>;
		no-map;
	};
	vision_apps_main_r5fss0_core0_memory_region: vision-apps-r5f-memory@a2100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa2100000 0x00 0x01f00000>;
		no-map;
	};
	vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a5000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa5000000 0x00 0x02000000>;
		no-map;
	};
	vision_apps_memory_region: vision-apps-dma-memory@a7000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xa7000000 0x00 0x06000000>;
		no-map;
	};
	vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@ad000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xad000000 0x00 0x00100000>;
		no-map;
	};
	vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@ad100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xad100000 0x00 0x03f00000>;
		no-map;
	};
	vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b1000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xb1000000 0x00 0x00100000>;
		no-map;
	};
	vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b1100000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xb1100000 0x00 0x03f00000>;
		no-map;
	};
	vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@b5000000 {
		compatible = "shared-dma-pool";
		reg = <0x00 0xb5000000 0x00 0x02800000>;
		no-map;
	};
	c7x_ddr_heaps_hi: c7x-ddr-heaps-hi@880000000 {
		compatible = "shared-dma-pool";
		reg = <0x08 0x80000000 0x00 0x20000000>;
		no-map;
	};
	vision_apps_shared_region: vision_apps_shared-memories {
		compatible = "dma-heap-carveout";
		reg = <0x08 0xa0000000 0x00 0x20000000>;
	};
    linux,cma {
        status = "disabled";
    };
    // linux_cma_region: linux-cma-buffers@8C0000000 {
    //     compatible = "shared-dma-pool";
    //     reusable;
    //     reg = <0x08 0xc0000000 0x00 0x10000000>;
    //     linux,cma-default;
    // };
};

&wkup_r5fss0_core0 {
	memory-region = <&vision_apps_wkup_r5fss0_core0_dma_memory_region>,
			<&vision_apps_wkup_r5fss0_core0_memory_region>;
};

&mcu_r5fss0_core0 {
	memory-region = <&vision_apps_mcu_r5fss0_core0_dma_memory_region>,
			<&vision_apps_mcu_r5fss0_core0_memory_region>;
};

&main_r5fss0_core0 {
	memory-region = <&vision_apps_main_r5fss0_core0_dma_memory_region>,
			<&vision_apps_main_r5fss0_core0_memory_region>;
};

&c7x_0 {
	memory-region = <&vision_apps_c71_0_dma_memory_region>,
			<&vision_apps_c71_0_memory_region>;
};

&c7x_1 {
	memory-region = <&vision_apps_c71_1_dma_memory_region>,
			<&vision_apps_c71_1_memory_region>;
};

I am running the following commands:

`source /opt/vision_apps/vision_apps_init.sh`
`/opt/vision_apps/run_app_single_cam.sh`

My camera driver fails to probe (because of reasons that are my own fault). After the probe fails, the application completely hangs.

It makes it to the return of the function `ImageSensor_RemoteServiceHandler`, and continues on app_single_cam until it tries to run `vxVerifyGraph`, at which point the application hangs indefinitely. Any future attempts to run an application will hang when it tries to communicate with the RTOS.

(If the system were functioning normally, I'd expect it to make it all the way to running* the graph, at which point it will simply not get an image and complain.)

0 Jared McArthur 15 days ago in reply to Stuart Burtner

TI__Mastermind 24590 points

Hi Stuart Burtner,

Can you share the output of sourcing the vision_apps_init.sh?

Best,
Jared

0 Stuart Burtner 15 days ago in reply to Jared McArthur

Intellectual 321 points

Jared,

See the output below:

root@j722s-evm:~# cd /opt/vision_apps/
root@j722s-evm:/opt/vision_apps# source ./vision_apps_init.sh 
root@j722s-evm:/opt/vision_apps# [MCU2_0]      4.697839 s: CIO: Init ... Done !!!
[MCU2_0]      4.697874 s: CPU is running FreeRTOS
[MCU2_0]      4.697885 s: APP: Init ... !!!
[MCU2_0]      4.697895 s: SCICLIENT: Init ... !!!
[MCU2_0]      4.697957 s: SCICLIENT: DMSC FW version [11.0.9--v11.00.09+ (Fancy Rat)]
[MCU2_0]      4.697973 s: SCICLIENT: DMSC FW revision 0xb  
[MCU2_0]      4.697987 s: SCICLIENT: DMSC FW ABI revision 4.0
[MCU2_0]      4.698000 s: SCICLIENT: Init ... Done !!!
[MCU2_0]      4.698011 s: UDMA: Init ... !!!
[MCU2_0]      4.698185 s: UDMA: Init ... Done !!!
[MCU2_0]      4.698201 s: MEM: Init ... !!!
[MCU2_0]      4.698214 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ b5800000 of size 33554432 bytes !!!
[MCU2_0]      4.698242 s: MEM: Init ... Done !!!
[MCU2_0]      4.698253 s: IPC: Init ... !!!
[MCU2_0]      4.698266 s: IPC: 4 CPUs participating in IPC !!!
[MCU2_0]      4.698447 s: IPC: Waiting for HLOS to be ready ... !!!
[MCU2_0]     16.059044 s: IPC: HLOS is ready !!!
[MCU2_0]     16.059104 s: IPC: Init ... Done !!!
[MCU2_0]     16.059120 s: APP: Syncing with 3 CPUs ... !!!
[MCU2_0]     16.059137 s: APP: Syncing with 3 CPUs ... Done !!!
[MCU2_0]     16.059151 s: REMOTE_SERVICE: Init ... !!!
[MCU2_0]     16.060067 s: REMOTE_SERVICE: Init ... Done !!!
[MCU2_0]     16.060084 s: FVID2: Init ... !!!
[MCU2_0]     16.060108 s: FVID2: Init ... Done !!!
[MCU2_0]     16.060370 s: DispApp_init() - DONE !!!
[MCU2_0]     16.061871 s: Display create complete!!
[MCU2_0]     16.061894 s: VHWA: VPAC Init ... !!!
[MCU2_0]     16.061906 s: SCICLIENT: Sciclient_pmSetModuleState module=219 state=2
[MCU2_0]     16.061987 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     16.062023 s: VHWA: LDC Init ... !!!
[MCU2_0]     16.062119 s: VHWA: LDC Init ... Done !!!
[MCU2_0]     16.062137 s: VHWA: MSC Init ... !!!
[MCU2_0]     16.062858 s: VHWA: MSC Init ... Done !!!
[MCU2_0]     16.062875 s: VHWA: VISS Init ... !!!
[MCU2_0]     16.063500 s: VHWA: VISS Init ... Done !!!
[MCU2_0]     16.063518 s: VHWA: FC Init ... !!!
[MCU2_0]     16.063556 s: VHWA: FC Init ... Done !!!
[MCU2_0]     16.063568 s: VHWA: VPAC Init ... Done !!!
[MCU2_0]     16.063580 s: VHWA: DMPAC: Init ... !!!
[MCU2_0]     16.063591 s: SCICLIENT: Sciclient_pmSetModuleState module=277 state=2
[MCU2_0]     16.063680 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     16.063692 s: VHWA: DOF Init ... !!!
[MCU2_0]     16.063799 s: VHWA: DOF Init ... Done !!!
[MCU2_0]     16.063814 s: VHWA: SDE Init ... !!!
[MCU2_0]     16.063889 s: VHWA: SDE Init ... Done !!!
[MCU2_0]     16.063901 s: VHWA: DMPAC: Init ... Done !!!
[MCU2_0]     16.063923 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
[MCU2_0]     16.063939 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
[MCU2_0]     16.063954 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
[MCU2_0]     16.064190 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.cmd_timeout_test on target MCU2-0
[MCU2_0]     16.064254 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.tiovx_overhead on target MCU2-0
[MCU2_0]     16.064297 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_sink on target MCU2-0
[MCU2_0]     16.064335 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_source on target MCU2-0
[MCU2_0]     16.064375 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_sink2 on target MCU2-0
[MCU2_0]     16.064413 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_source2 on target MCU2-0
[MCU2_0]     16.064451 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_intermediate on target MCU2-0
[MCU2_0]     16.064492 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target MCU2-0
[MCU2_0]     16.064532 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_source_error on target MCU2-0
[MCU2_0]     16.064573 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_source_obj_array on target MCU2-0
[MCU2_0]     16.064614 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target MCU2-0
[MCU2_0]     16.064655 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_intermediate on target MCU2-0
[MCU2_0]     16.064695 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_source on target MCU2-0
[MCU2_0]     16.064734 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_sink on target MCU2-0
[MCU2_0]     16.064772 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.test_target on target MCU2-0
[MCU2_0]     16.064813 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.image_intermediate on target MCU2-0
[MCU2_0]     16.064856 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.ext.obj_array_split on target MCU2-0
[MCU2_0]     16.064941 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 
[MCU2_0]     16.064998 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 
[MCU2_0]     16.065062 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 
[MCU2_0]     16.065119 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 
[MCU2_0]     16.065204 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 
[MCU2_0]     16.065269 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 
[MCU2_0]     16.065325 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 
[MCU2_0]     16.065383 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 
[MCU2_0]     16.065450 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 
[MCU2_0]     16.065509 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 
[MCU2_0]     16.065569 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 
[MCU2_0]     16.065625 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 
[MCU2_0]     16.065683 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 
[MCU2_0]     16.065740 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 
[MCU2_0]     16.065798 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 
[MCU2_0]     16.065892 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 
[MCU2_0]     16.065915 s:  VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!!
[MCU2_0]     16.065933 s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[MCU2_0]     16.065946 s: APP: OpenVX Target kernel init ... !!!
[MCU2_0]     16.071406 s: APP: OpenVX Target kernel init ... Done !!!
[MCU2_0]     16.071427 s: UDMA: Init for CSITX/CSIRX ... !!!
[MCU2_0]     16.071580 s: UDMA: Init for CSITX/CSIRX ... Done !!!
[MCU2_0]     16.071597 s: CSI2RX: Init ... !!!
[MCU2_0]     16.071607 s: SCICLIENT: Sciclient_pmSetModuleState module=182 state=2
[MCU2_0]     16.071643 s: SCICLIENT: ERROR: Sciclient_pmSetModuleState failed
[MCU2_0]     16.071657 s: SCICLIENT: Sciclient_pmSetModuleState module=247 state=2
[MCU2_0]     16.071710 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     16.071723 s: SCICLIENT: Sciclient_pmSetModuleState module=185 state=2
[MCU2_0]     16.071763 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     16.071775 s: SCICLIENT: Sciclient_pmSetModuleState module=251 state=2
[MCU2_0]     16.071814 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     16.071977 s: CSI2RX: Init ... Done !!!
[MCU2_0]     16.071991 s: CSI2TX: Init ... !!!
[MCU2_0]     16.072001 s: SCICLIENT: Sciclient_pmSetModuleState module=250 state=2
[MCU2_0]     16.072059 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     16.072072 s: SCICLIENT: Sciclient_pmSetModuleState module=238 state=2
[MCU2_0]     16.072115 s: SCICLIENT: Sciclient_pmSetModuleState success
[MCU2_0]     16.072127 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=250 clk=3 freq=16000000
[MCU2_0]     16.072184 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     16.072197 s: SCICLIENT: Sciclient_pmSetModuleClkFreq module=250 clk=4 freq=500000000
[MCU2_0]     16.072246 s: SCICLIENT: Sciclient_pmSetModuleClkFreq success
[MCU2_0]     16.072272 s: CSI2TX: Init ... Done !!!
[MCU2_0]     16.072284 s: ISS: Init ... !!!
[MCU2_0]     16.072306 s: IssSensor_Init ... Done !!!
[MCU2_0]     16.072352 s: IttRemoteServer_Init ... Done !!!
[MCU2_0]     16.072364 s: ISS: Init ... Done !!!
[MCU2_0]     16.072377 s: VISS REMOTE SERVICE: Init ... !!!
[MCU2_0]     16.072413 s: VISS REMOTE SERVICE: Init ... Done !!!
[MCU2_0]     16.072426 s: UDMA Copy: Init ... !!!
[MCU2_0]     16.072670 s: UDMA Copy: Init ... Done !!!
[MCU2_0]     16.072693 s: APP: Init ... Done !!!
[MCU2_0]     16.072705 s: APP: Run ... !!!
[MCU2_0]     16.072715 s: IPC: Starting echo test ...
[MCU2_0]     16.072778 s: APP: Run ... Done !!!
[MCU2_0]     16.073444 s: IPC: Echo status: a530-0[.] main-r5f0-0[s] c75ss0[.] c75ss1[P] 
[MCU2_0]     16.073832 s: IPC: Echo status: a530-0[.] main-r5f0-0[s] c75ss0[P] c75ss1[P] 
[C7x_1 ]      5.232364 s: CIO: Init ... Done !!!
[C7x_1 ]      5.232382 s: CPU is running FreeRTOS
[C7x_1 ]      5.232392 s: APP: Init ... !!!
[C7x_1 ]      5.232402 s: SCICLIENT: Init ... !!!
[C7x_1 ]      5.232462 s: SCICLIENT: DMSC FW version [11.0.9--v11.00.09+ (Fancy Rat)]
[C7x_1 ]      5.232479 s: SCICLIENT: DMSC FW revision 0xb  
[C7x_1 ]      5.232492 s: SCICLIENT: DMSC FW ABI revision 4.0
[C7x_1 ]      5.232505 s: SCICLIENT: Init ... Done !!!
[C7x_1 ]      5.232517 s: UDMA: Init ... !!!
[C7x_1 ]      5.232541 s: UDMA: Init ... Done !!!
[C7x_1 ]      5.232554 s: MEM: Init ... !!!
[C7x_1 ]      5.232565 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 108000000 of size 67108864 bytes !!!
[C7x_1 ]      5.232589 s: MEM: Init ... Done !!!
[C7x_1 ]      5.232600 s: IPC: Init ... !!!
[C7x_1 ]      5.232610 s: IPC: 4 CPUs participating in IPC !!!
[C7x_1 ]      5.232891 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_1 ]     15.305774 s: IPC: HLOS is ready !!!
[C7x_1 ]     15.305839 s: IPC: Init ... Done !!!
[C7x_1 ]     15.305854 s: APP: Syncing with 3 CPUs ... !!!
[C7x_1 ]     16.059139 s: APP: Syncing with 3 CPUs ... Done !!!
[C7x_1 ]     16.059156 s: REMOTE_SERVICE: Init ... !!!
[C7x_1 ]     16.059293 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_1 ]     16.059337 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
[C7x_1 ]     16.059357 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
[C7x_1 ]     16.059375 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
[C7x_1 ]     16.059905 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP_C7-1
[C7x_1 ]     16.059949 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_sink on target DSP_C7-1
[C7x_1 ]     16.059991 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_source on target DSP_C7-1
[C7x_1 ]     16.060032 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_sink2 on target DSP_C7-1
[C7x_1 ]     16.060071 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_source2 on target DSP_C7-1
[C7x_1 ]     16.060111 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_intermediate on target DSP_C7-1
[C7x_1 ]     16.060153 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target DSP_C7-1
[C7x_1 ]     16.060195 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_source_error on target DSP_C7-1
[C7x_1 ]     16.060237 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_source_obj_array on target DSP_C7-1
[C7x_1 ]     16.060279 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target DSP_C7-1
[C7x_1 ]     16.060321 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_intermediate on target DSP_C7-1
[C7x_1 ]     16.060363 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_source on target DSP_C7-1
[C7x_1 ]     16.060405 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_sink on target DSP_C7-1
[C7x_1 ]     16.060447 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.test_target on target DSP_C7-1
[C7x_1 ]     16.060488 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.image_intermediate on target DSP_C7-1
[C7x_1 ]     16.060530 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.multi_in_out on target DSP_C7-1
[C7x_1 ]     16.060572 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.test_target on target DSP_C7-1
[C7x_1 ]     16.060615 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.tiovx_overhead on target DSP_C7-1
[C7x_1 ]     16.060729 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 
[C7x_1 ]     16.060865 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 
[C7x_1 ]     16.060994 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 
[C7x_1 ]     16.061123 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 
[C7x_1 ]     16.061251 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 
[C7x_1 ]     16.061380 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 
[C7x_1 ]     16.061509 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 
[C7x_1 ]     16.061637 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 
[C7x_1 ]     16.061663 s:  VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!!
[C7x_1 ]     16.061705 s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[C7x_1 ]     16.061735 s: APP: OpenVX Target kernel init ... !!!
[C7x_1 ]     16.062255 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_1 ]     16.062274 s: APP: Init ... Done !!!
[C7x_1 ]     16.062287 s: APP: Run ... !!!
[C7x_1 ]     16.062299 s: IPC: Starting echo test ...
[C7x_1 ]     16.062429 s: APP: Run ... Done !!!
[C7x_1 ]     16.074059 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[s] c75ss1[.] 
[C7x_1 ]     16.074097 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[s] c75ss1[P] 
[C7x_2 ]      5.768927 s: CIO: Init ... Done !!!
[C7x_2 ]      5.768945 s: CPU is running FreeRTOS
[C7x_2 ]      5.768956 s: APP: Init ... !!!
[C7x_2 ]      5.768967 s: SCICLIENT: Init ... !!!
[C7x_2 ]      5.769026 s: SCICLIENT: DMSC FW version [11.0.9--v11.00.09+ (Fancy Rat)]
[C7x_2 ]      5.769043 s: SCICLIENT: DMSC FW revision 0xb  
[C7x_2 ]      5.769055 s: SCICLIENT: DMSC FW ABI revision 4.0
[C7x_2 ]      5.769068 s: SCICLIENT: Init ... Done !!!
[C7x_2 ]      5.769080 s: UDMA: Init ... !!!
[C7x_2 ]      5.769104 s: UDMA: Init ... Done !!!
[C7x_2 ]      5.769117 s: MEM: Init ... !!!
[C7x_2 ]      5.769128 s: MEM: Created heap (DDR_LOCAL_MEM, id=0, flags=0x00000004) @ 118000000 of size 67108864 bytes !!!
[C7x_2 ]      5.769152 s: MEM: Init ... Done !!!
[C7x_2 ]      5.769162 s: IPC: Init ... !!!
[C7x_2 ]      5.769174 s: IPC: 4 CPUs participating in IPC !!!
[C7x_2 ]      5.769451 s: IPC: Waiting for HLOS to be ready ... !!!
[C7x_2 ]     15.414304 s: IPC: HLOS is ready !!!
[C7x_2 ]     15.414370 s: IPC: Init ... Done !!!
[C7x_2 ]     15.414384 s: APP: Syncing with 3 CPUs ... !!!
[C7x_2 ]     16.059139 s: APP: Syncing with 3 CPUs ... Done !!!
[C7x_2 ]     16.059155 s: REMOTE_SERVICE: Init ... !!!
[C7x_2 ]     16.059340 s: REMOTE_SERVICE: Init ... Done !!!
[C7x_2 ]     16.059364 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
[C7x_2 ]     16.059384 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
[C7x_2 ]     16.059409 s:  VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
[C7x_2 ]     16.059976 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP_C7-2
[C7x_2 ]     16.060021 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_sink on target DSP_C7-2
[C7x_2 ]     16.060063 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_source on target DSP_C7-2
[C7x_2 ]     16.060105 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_sink2 on target DSP_C7-2
[C7x_2 ]     16.060147 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_source2 on target DSP_C7-2
[C7x_2 ]     16.060189 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.scalar_intermediate on target DSP_C7-2
[C7x_2 ]     16.060231 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_intermediate_2 on target DSP_C7-2
[C7x_2 ]     16.060279 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_source_error on target DSP_C7-2
[C7x_2 ]     16.060325 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_source_obj_array on target DSP_C7-2
[C7x_2 ]     16.060369 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.scalar_sink_obj_array on target DSP_C7-2
[C7x_2 ]     16.060413 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_intermediate on target DSP_C7-2
[C7x_2 ]     16.060456 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_source on target DSP_C7-2
[C7x_2 ]     16.060499 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.pyramid_sink on target DSP_C7-2
[C7x_2 ]     16.060542 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.test_target on target DSP_C7-2
[C7x_2 ]     16.060584 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.capture.image_intermediate on target DSP_C7-2
[C7x_2 ]     16.060626 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.test_target on target DSP_C7-2
[C7x_2 ]     16.060711 s:  VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel com.ti.test_kernels.tiovx_overhead on target DSP_C7-2
[C7x_2 ]     16.060866 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2 
[C7x_2 ]     16.060997 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_2 
[C7x_2 ]     16.061126 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_3 
[C7x_2 ]     16.061255 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_4 
[C7x_2 ]     16.061390 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_5 
[C7x_2 ]     16.061520 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_6 
[C7x_2 ]     16.061648 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_7 
[C7x_2 ]     16.061736 s:  VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-2_PRI_8 
[C7x_2 ]     16.061761 s:  VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!!
[C7x_2 ]     16.061780 s:  VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[C7x_2 ]     16.061793 s: APP: OpenVX Target kernel init ... !!!
[C7x_2 ]     16.062329 s: APP: OpenVX Target kernel init ... Done !!!
[C7x_2 ]     16.062389 s: APP: Init ... Done !!!
[C7x_2 ]     16.062432 s: APP: Run ... !!!
[C7x_2 ]     16.062444 s: IPC: Starting echo test ...
[C7x_2 ]     16.062573 s: APP: Run ... Done !!!
[C7x_2 ]     16.073518 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[.] c75ss1[s] 
[C7x_2 ]     16.073983 s: IPC: Echo status: a530-0[.] main-r5f0-0[P] c75ss0[P] c75ss1[s]

+1 Jared McArthur 15 days ago in reply to Stuart Burtner

TI__Mastermind 24590 points

Hi Stuart Burtner,

The memory map that you attached is identical to the memory map that is currently within the SDK. Was that intentional?

Why did you comment out the linux_cma_region?

Please go over the following thread which did what you are trying to accomplish: TDA4VEN-Q1: DDR-4GB debug

This app note can also help: https://www.ti.com/lit/ab/spradp3/spradp3.pdf

Best,
Jared

0 Stuart Burtner 15 days ago in reply to Jared McArthur

Intellectual 321 points

Jared,

Thank you for the app note - i'll check it out tomorrow morning :)

It should not be identical - I have moved the location of the C7x high heap / the shared memory.

I have tried with and without the linux_cma_region and saw no change. I was experimenting with things. The CMA reservation is massive relative to our remaining available memory so I assumed it should probably at least be downsized.

Below is a diff of what was changed in `gen_linker_mem_map.py` from the base SDK:

diff --git a/platform/j722s/rtos/gen_linker_mem_map.py b/platform/j722s/rtos/gen_linker_mem_map.py
index 18a008d5..ad834c02 100755
--- a/platform/j722s/rtos/gen_linker_mem_map.py
+++ b/platform/j722s/rtos/gen_linker_mem_map.py
@@ -154,13 +154,14 @@ c7x_2_l2_aux_as_l1_size  = 16*KB;
 #
 # DDR memory allocation for various CPUs
 #
-mcu1_0_ddr_ipc_addr = ddr_mem_addr;
+ddr_ipc_start_addr = ddr_mem_addr + 0x01000000;
+mcu1_0_ddr_ipc_addr = ddr_ipc_start_addr;
 mcu1_0_ddr_resource_table_addr = mcu1_0_ddr_ipc_addr + linux_ddr_ipc_size;
 mcu1_0_ddr_ipc_tracebuf_addr = mcu1_0_ddr_resource_table_addr + linux_ddr_resource_table_size;
 mcu1_0_ddr_addr = mcu1_0_ddr_ipc_tracebuf_addr + linux_ddr_ipc_trace_size;
 mcu1_0_ddr_size = 16*MB - (mcu1_0_ddr_addr-mcu1_0_ddr_ipc_addr);
 
-mcu2_0_ddr_ipc_addr = mcu1_0_ddr_addr + mcu1_0_ddr_size + 16*MB;
+mcu2_0_ddr_ipc_addr = mcu1_0_ddr_addr + mcu1_0_ddr_size;
 mcu2_0_ddr_resource_table_addr = mcu2_0_ddr_ipc_addr + linux_ddr_ipc_size;
 mcu2_0_ddr_ipc_tracebuf_addr = mcu2_0_ddr_resource_table_addr + linux_ddr_resource_table_size;
 mcu2_0_ddr_addr = mcu2_0_ddr_ipc_tracebuf_addr + linux_ddr_ipc_trace_size;
@@ -272,7 +273,7 @@ c7x_2_1_ddr_local_heap_addr = c7x_1_ddr_local_heap_addr;
 c7x_2_1_ddr_scratch_addr = c7x_1_ddr_scratch_addr;
 
 # Shared memory for DMA Buf FD carveout (located in high mem)
-ddr_shared_mem_addr_phys  = 0x900000000;
+ddr_shared_mem_addr_phys  = ddr_mem_addr_hi_phys + total_c7x_ddr;
 
 #
 # Create memory section based on addr and size defined above, including
@@ -656,6 +657,6 @@ LinkerCmdFile(mcu2_0_mmap, "./mcu2_0/linker_mem_map.cmd").export();
 
 HtmlMmapTable(html_mmap, "./system_memory_map.html").export();
 
-CHeaderFile(c_header_mmap, 0x880000000, 0x100000000, "./app_mem_map.h").export();
+CHeaderFile(c_header_mmap, ddr_mem_addr_hi_phys, ddr_mem_addr_hi, "./app_mem_map.h").export();
 
 DtsFile(dts_mmap, "./k3-j722s-rtos-memory-map.dtsi").export();

and below is the change in the device tree file (for linux, but u-boot is the same)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index ff71fe5ef68d..4b1af2128b37 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -31,9 +31,9 @@ chosen {
        };
 
        memory@80000000 {
-               /* 8G RAM */
+               /* 4G RAM */
                reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000001 0x80000000>;
+                     <0x00000008 0x80000000 0x00000000 0x80000000>;
                device_type = "memory";
                bootph-pre-ram;
        };
@@ -47,7 +47,7 @@ reserved_memory: reserved-memory {
                linux,cma {
                        compatible = "shared-dma-pool";
                        reusable;
-                       size = <0x00 0x38000000>;
+                       size = <0x00 0x10000000>;
                        linux,cma-default;
                };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-rtos-memory-map.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-rtos-memory-map.dtsi
index 1e79eef6a22c..814057ae9088 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-rtos-memory-map.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-rtos-memory-map.dtsi
@@ -130,15 +130,15 @@ c7x_ddr_heaps_hi: c7x-ddr-heaps-hi@880000000 {
        };
        vision_apps_shared_region: vision_apps_shared-memories {
                compatible = "dma-heap-carveout";
-               reg = <0x09 0x00000000 0x00 0x20000000>;
+               reg = <0x08 0xa0000000 0x00 0x20000000>;
        };
     linux,cma {
         status = "disabled";
     };
-    linux_cma_region: linux-cma-buffers@980000000 {
+    linux_cma_region: linux-cma-buffers@8C0000000 {
         compatible = "shared-dma-pool";
         reusable;
-        reg = <0x09 0x80000000 0x00 0x38000000>;
+        reg = <0x08 0xc0000000 0x00 0x10000000>;
         linux,cma-default;
     };
 };

u-boot - for completeness sake:

diff --git a/arch/arm/dts/k3-j722s-rtos-memory-map.dtsi b/arch/arm/dts/k3-j722s-rtos-memory-map.dtsi
index a352f1ebbc6..8553ae95c98 100644
--- a/arch/arm/dts/k3-j722s-rtos-memory-map.dtsi
+++ b/arch/arm/dts/k3-j722s-rtos-memory-map.dtsi
@@ -85,57 +85,62 @@
                reg = <0x00 0xa2100000 0x00 0x01f00000>;
                no-map;
        };
-       vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a6000000 {
+       vision_apps_rtos_ipc_memory_region: vision-apps-rtos-ipc-memory-region@a5000000 {
                compatible = "shared-dma-pool";
-               reg = <0x00 0xa6000000 0x00 0x02000000>;
+               reg = <0x00 0xa5000000 0x00 0x02000000>;
                no-map;
        };
-       vision_apps_memory_region: vision-apps-dma-memory@a8000000 {
+       vision_apps_memory_region: vision-apps-dma-memory@a7000000 {
                compatible = "shared-dma-pool";
-               reg = <0x00 0xa8000000 0x00 0x06000000>;
+               reg = <0x00 0xa7000000 0x00 0x06000000>;
                no-map;
        };
-       vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@ae000000 {
+       vision_apps_c71_0_dma_memory_region: vision-apps-c71-dma-memory@ad000000 {
                compatible = "shared-dma-pool";
-               reg = <0x00 0xae000000 0x00 0x00100000>;
+               reg = <0x00 0xad000000 0x00 0x00100000>;
                no-map;
        };
-       vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@ae100000 {
+       vision_apps_c71_0_memory_region: vision-apps-c71_0-memory@ad100000 {
                compatible = "shared-dma-pool";
-               reg = <0x00 0xae100000 0x00 0x03f00000>;
+               reg = <0x00 0xad100000 0x00 0x03f00000>;
                no-map;
        };
-       vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b2000000 {
+       vision_apps_c71_1_dma_memory_region: vision-apps-c71_1-dma-memory@b1000000 {
                compatible = "shared-dma-pool";
-               reg = <0x00 0xb2000000 0x00 0x00100000>;
+               reg = <0x00 0xb1000000 0x00 0x00100000>;
                no-map;
        };
-       vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b2100000 {
+       vision_apps_c71_1_memory_region: vision-apps-c71_1-memory@b1100000 {
                compatible = "shared-dma-pool";
-               reg = <0x00 0xb2100000 0x00 0x03f00000>;
+               reg = <0x00 0xb1100000 0x00 0x03f00000>;
                no-map;
        };
-       vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@b6000000 {
+       vision_apps_core_heaps_lo: vision-apps-core-heap-memory-lo@b5000000 {
                compatible = "shared-dma-pool";
-               reg = <0x00 0xb6000000 0x00 0x02800000>;
+               reg = <0x00 0xb5000000 0x00 0x02800000>;
                no-map;
        };
-       vision_apps_core_heaps_hi: vision-apps-core-heap-memory-hi@880000000 {
+       c7x_ddr_heaps_hi: c7x-ddr-heaps-hi@880000000 {
                compatible = "shared-dma-pool";
                reg = <0x08 0x80000000 0x00 0x20000000>;
                no-map;
        };
        vision_apps_shared_region: vision_apps_shared-memories {
                compatible = "dma-heap-carveout";
-               reg = <0x09 0x00000000 0x00 0x20000000>;
+               reg = <0x08 0xa0000000 0x00 0x20000000>;
        };
+       // vision_apps_core_heaps_hi: vision-apps-core-heap-memory-hi@880000000 {
+       //      compatible = "shared-dma-pool";
+       //      reg = <0x08 0x80000000 0x00 0x20000000>;
+       //      no-map;
+       // };
     linux,cma {
         status = "disabled";
     };
-    linux_cma_region: linux-cma-buffers@980000000 {
+    linux_cma_region: linux-cma-buffers@8C0000000 {
         compatible = "shared-dma-pool";
         reusable;
-        reg = <0x09 0x80000000 0x00 0x38000000>;
+        reg = <0x08 0xC0000000 0x00 0x10000000>;
         linux,cma-default;
     };
 };
diff --git a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
index e362bfbb655..3fb51dc62bd 100644
--- a/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
+++ b/dts/upstream/src/arm64/ti/k3-j722s-evm.dts
@@ -30,9 +30,12 @@
        };
 
        memory@80000000 {
+               // /* 4G RAM */
+               // reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
+               //        <0x00000004 0x80000000 0x00000001 0x80000000>;
                /* 8G RAM */
                reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
-                     <0x00000008 0x80000000 0x00000001 0x80000000>;
+                     <0x00000008 0x80000000 0x00000000 0x80000000>;
                device_type = "memory";
                bootph-pre-ram;
        };
@@ -46,7 +49,7 @@
                linux,cma {
                        compatible = "shared-dma-pool";
                        reusable;
-                       size = <0x00 0x38000000>;
+                       size = <0x00 0x10000000>;
                        linux,cma-default;
                };