This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6657: About EMIF16 operation

Part Number: TMS320C6657

Hi experts,

Chapter 2.4 of the SPUGZ3A "Keystone Architecture External Memory Interface (EMIF16) User Guide" shows the following: 

image.png

Q1. It is noted that each of the above two modes can be enabled. In other words, there are actually three modes of operation: We strobe mode, Select Strobe mode, and operation mode with both disabled(Extended Wait Mode?). 

This question assumes that there is a third mode of operation in the question above. In Table 5-17 of the TMS320C5557 data sheet, No.4 and No.5 are listed for the CE-OE timing with SS=0 and SS=1, but there is no difference in the values. There are also two types of No.16 and No.17, but there is no difference in the values.

From the EMIF16 User Guide, we understood that the difference in EMIFCE operation as follows:

  • In Asynchronous reads in SS Mode in section 2.5.5.1, EMIFCE and EMIFOE are low when Strobe period starts.
  • In Asynchronous reads in Chapter 2.5.4.1 (in which both SS Mode and we Mode are disabled), EMIFCE becomes low wQ2hen the Setup period is started.

Q2. Can you tell us the difference in the timing of read and write cycles when SS Mode is enabled and disabled? 

Regards,
Hiromu

  • Hi Hiromu,

    Let me check this and get back to you within a day.

    Regards,

    Betsy Varughese

  • Hi Hiromu,

    Q1. It is noted that each of the above two modes can be enabled. In other words, there are actually three modes of operation: We strobe mode, Select Strobe mode, and operation mode with both disabled(Extended Wait Mode?). 

    Could you please refer this :  Questions about Keystone EMIF16 documentation


    EMIF16 supports three asynchronous operating states: Normal mode (ss=0), Select Strobe (SS) mode (ss=1), and WE Strobe mode (CE3 only). In Normal mode, EMIFCE remains active throughout the entire access, whereas in SS mode it is asserted only during the strobe phase.

    Extended Wait Mode is not a separate operating state; it is a timing extension feature that can be used in conjunction with these modes.

    Q2. Can you tell us the difference in the timing of read and write cycles when SS Mode is enabled and disabled? 

    In SS=0, EMIFCE goes LOW at the start of SETUP — R_SETUP clock cycles before EMIFOE or EMIFWE asserts — and stays LOW for the entire access. In SS=1, EMIFCE and EMIFOE go LOW simultaneously at the start of STROBE and both go HIGH simultaneously at the start of HOLD, so CE is active only for the strobe duration with zero gap between CE and OE.

    Table 5-17 in datasheet shows the same formula for SS=0 and SS=1 because those parameters measure the pin-level delta between CE and OE transitions, which is the same in both modes. The real difference — which phase CE activates in — is visible in the waveform diagrams (Figure 2-4/2-5 vs Figure 2-6/2-7 in SPUGZ3A), not as a different timing value in the table.

    Regards,
    Shabary S Sundar