Part Number: TDA4VH-Q1
Hello TI forum!
Could you confirm that the SGMII interfaces on TDA4VH-Q1 supports clock recovery from the SGMII receive data signal, i.e. do not require a separate SGMII receive clock signal from the external PHY for that?
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Part Number: TDA4VH-Q1
Hello TI forum!
Could you confirm that the SGMII interfaces on TDA4VH-Q1 supports clock recovery from the SGMII receive data signal, i.e. do not require a separate SGMII receive clock signal from the external PHY for that?
Hello!
Thank you for your answer!
Could you elaborate a bit about the internal 100MHz clock you mention? What is it used or intended for now when it is established that the SoC itself has built -in clock recovery? Or is this internal reference clock a part of the SoC´s standalone clock recovery functionality?
Hi Peter,
This is the internal reference clock which is required to generate the required transmitter baud rate of the protocol in the high speed SERDES.
It can also be driven out of the SERDES_REFCLK pins to sync b/w the SoC and the PHY if needed instead of using an external oscillator or ext reference clock.