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Original question:

TDA4VE-Q1: TDA LPDDR4_Read Eye Mask Specification

AM62D-Q1: Read Eye Mask Specification

O.H
Mastermind 7170 points

Part Number: AM62D-Q1

Hi experts,

Our customer is designing a board with AM62D and conducting LPDDR4 simulation. They are designing with reference to "AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines  SPRAD66B". The design follows Table 2-6. CK0 and ADDR_CTRL Routing Specifications and Table 2-7. Data Group Routing Specifications, but does not meet the requirements of Table 3-3. LPDDR4 Eye Mask Definitions/Requirements. 
 
Read_EYE.png
 
Q1: They think the eye opening of 0.66UI during READ is quite strict, but is there any way to relax this requirement?
Q2: We understand that for AM62D, the timing of DQS for each Byte Lane can be adjusted within the controller during Read, but the delay adjustment for each DQ signal within a Byte Lane cannot be done. Is this correct?
If it is possible to adjust each DQ signal individually, the above results would pass.
 
Best regards,
O.H
  • 0
    Mastermind 7170 points

    Hi experts,

    Thsi is additional information.

    Operation is assumed at 3733 Mbps. The specification values on the READ side (AM62D-Q1) are strict. Since LPDDR4 does not specify values equivalent to the setup and hold times of normal signals, they refer to the Eye Mask specification values of the AM62D-Q1 (time axis: 0.66 UI, voltage axis: 140 mV). The attached waveform is simulated including crosstalk, so it contains a lot of jitter components.
    Best regards,
    O.H
  • 0 in reply to O.H
    Mastermind 7170 points

    Hi experts,

    Q2 clarification:

    Q2-1: Is it possible for the controller to perform deskew for each bit?
    Q2-2: Or is it possible for the controller to perform deskew for each Byte Lane?

    If it is case 2-1, it is sufficient to adjust the wire length within the Byte Lane according to "SPRAD66B". However, in case 2-2, it is necessary to make the wiring within the Byte Lane almost equal length (equal delay) for it to work.

    Best regards,
    O.H
  • +1 in reply to O.H
    TI__Guru* 95181 points

    Q1. We can't relax this requirement

    Q2-1 : the training algorithm on silicon will perform per-bit deskew for each bit.  Note that we recently relaxed the length matching requirements as the per-bit deskew can handle certain amount of mismatched traces within a byte.  See LP4_DRS5 and LP4_ACRS6.  Note these are skews within each byte.

    Thus, as long as you follow the guidelines in SPRAD66B, the DDR init and training will optimize both write and read eyes

    Regards,

    James

  • 0 in reply to JJD
    Mastermind 7170 points

    Hi James,

    Sorry for late reply. Thank you for your support.

    We understood. If any further questions arise, I will create a new thread.

    Best regards,
    O.H