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Original question:

AM6442: Watchdog Timer Issue on SR2.0 Silicon

AM620-Q1: ESM configuration error when using SBL boot

Shibi MAnoharan
Prodigy 130 points

Part Number: AM620-Q1

Hello,

        I am trying to setup main RTI0 as watchdog which must be initialized at early boot stage to cause a system reset if the linux kernel hangs. This works when tested with SPL boot flow. But, with SBL boot flow watchdog timeout is not triggering a reset. Watchdog configuration is same for both SPL and SBL. I suspect the ESM configuration which is done correctly in SPL while it is not in SBL. 

 

Should the ESM init be done only by R5 core?

If that's the case the tispl.bin in SPL might be doing the initialization.

Is it not the case for SBL boot flow?

Is there any reference for configuring the watchdog and ESM with SBL boot flow?

 

 

SYSFW Firmware Version 11.1.2--v11.01.02 (Fancy Rat)
SYSFW Firmware revision 0xb
SYSFW ABI revision 4.0

Loading Image from A
[BOOTLOADER_PROFILE] Boot Media       : FLASH
[BOOTLOADER_PROFILE] Boot Media Clock : 166.667 MHz
[BOOTLOADER_PROFILE] Boot Image Size  : 230 KB
[BOOTLOADER_PROFILE] Cores present    :
m4f0-0
r5f0-0
[BOOTLOADER PROFILE] System_init                      :      29129us
[BOOTLOADER PROFILE] Board_init                       :          0us
[BOOTLOADER PROFILE] Drivers_open                     :        209us
[BOOTLOADER PROFILE] Board_driversOpen                :        120us
[BOOTLOADER PROFILE] Sciclient Get Version            :      10203us
[BOOTLOADER PROFILE] App_waitForMcuPbist              :        102us
[BOOTLOADER PROFILE] App_waitForMcuLbist              :       7689us
[BOOTLOADER PROFILE] App_loadImages                   :      11075us
[BOOTLOADER PROFILE] App_loadSelfcoreImage            :      11136us
[BOOTLOADER_PROFILE] SBL Total Time Taken             :      69667us

Image loading done, switching to application ...
Starting MCU-m4f and 2nd stage bootloader

SYSFW Firmware Version 11.1.2--v11.01.02 (Fancy Rat)
SYSFW Firmware revision 0xb
SYSFW ABI revision 4.0

Loading Image from A
[BOOTLOADER_PROFILE] Boot Media       : FLASH
[BOOTLOADER_PROFILE] Boot Media Clock : 166.667 MHz
[BOOTLOADER_PROFILE] Boot Image Size  : 1107 KB
[BOOTLOADER_PROFILE] Cores present    :
r5f0-0
a530-0
[BOOTLOADER PROFILE] System_init                      :       2806us
[BOOTLOADER PROFILE] Board_init                       :          1us
[BOOTLOADER PROFILE] Drivers_open                     :        270us
[BOOTLOADER PROFILE] Board_driversOpen                :        130us
[BOOTLOADER PROFILE] Sciclient Get Version            :      10284us
[BOOTLOADER PROFILE] App_loadSelfcoreImage            :      14881us
[BOOTLOADER PROFILE] App_loadLinuxImages              :      55059us
[BOOTLOADER_PROFILE] SBL Total Time Taken             :      83434us

Image loading done, switching to application ...
Starting linux and RTOS/Baremetal applications
NOTICE:  BL31: v2.11.0(release):T7RX_BOOT_2026.1.0
NOTICE:  BL31: Built : 14:56:24, Apr  6 2026
I/TC:
I/TC: OP-TEE version: T7RX_BOOT_2026.1.0 (gcc version 13.3.0 (Buildroot 2024.02.6)) #1 Mon Apr  6 09:26:31 UTC 2026 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check https://optee.readthedocs.io/en/latest/architecture/porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.2--v11.01.02 (Fancy Rat)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2025.04-00012-ge81f00002473-dirty (Apr 07 2026 - 15:55:43 +0530)
Checking for IO isolation
SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.2--v11.01.02 (Fancy Rat)')
esm main init failed: -96
esm mcu init failed: -96
SPL initial stack usage: 1952 bytes
Trying to boot from SPI
Boot Region A
Authentication passed
Authentication passed

  • 0
    TI__Mastermind 28426 points

    HI,

    Shibi MAnoharan said:
    I suspect the ESM configuration which is done correctly in SPL while it is not in SBL. 

    You should ensure that the ESM and Wdg are disabled in the linux device tree if you are configuring it from R5F core. 

    Shibi MAnoharan said:
    Is there any reference for configuring the watchdog and ESM with SBL boot flow?

    I am attaching the example I previously created for AM62Ax with MCU RTI0 integrated in SBL Null. The code should be very similar for AM62Ax as most of the APIs are same. You check this for reference. 

    SBL_NULL.zip

    Regards,

    Nihar Potturu

  • 0 in reply to Nihar Potturu
    Prodigy 130 points

    Hi Nihar,

            Thanks for your reply. This example provides a good baseline. I will try to implement this in R5F binary loaded by SBL. One main difference is that I am planning to use one of the Main RTIs to achieve this. So, I have to configure the MAIN ESM to generate a system reset when watchdog timeout occurs. Could this be accomplished by using R5F application? I will leave the watchdog configuration to u-boot.

  • 0 in reply to Shibi MAnoharan
    TI__Mastermind 28426 points

    Hi,

    Shibi MAnoharan said:
    So, I have to configure the MAIN ESM to generate a system reset when watchdog timeout occurs. Could this be accomplished by using R5F application? I

    Yes, the init sequence will be very similar. You just have to enable the Main ESM instead of the MCU ESM and enable the RTI0 event. 

    Please ensure the 17th bit of WKUP_MMR0_RST_CTRL register is set to 0 so that the ESM module can trigger an SoC reset when the Wdg expires.

    Regards,

    Nihar Potturu

  • 0 in reply to Nihar Potturu
    Prodigy 130 points

    Hi Nihar,

          Another question here. Are the ESM registers not configurable by other cores rather than the R5F? Why they must be configured only by R5F core?

  • 0 in reply to Shibi MAnoharan
    TI__Mastermind 28426 points

    Hi,

    Shibi MAnoharan said:
          Another question here. Are the ESM registers not configurable by other cores rather than the R5F? Why they must be configured only by R5F core?

    SDL is usually used to configure the ESM module. SDL is supported on M4F and R5F cores. You can use either M4F or R5F cores for configuring ESM. Since SBL runs on R5F, the example shared had ESM configuration from R5F.

    Regards,
    Nihar Potturu