Part Number: AM62A7
We are using the SDK-11.01.00 for our AM62A7 processor based board. Our board has the 1GB of DDR. So, we understand that we have to change the Reserved memory map for our board as it has 1GB DDR instead 4GB DDR.
We made reserve memory map change as mentioned in the FIRMWARE BUILDER SDK. Below is the screenshot of the memory map that we have changed.
vision_apps/platform/am62a/rtos/gen_linker_mem_map.py file change in the FIRMWARE BUILDER SDK
diff --git a/vision_apps/platform/am62a/rtos/gen_linker_mem_map.py b/vision_apps/platform/am62a/rtos/gen_linker_mem_map.py
index 2b00d6220..a1ee9e135 100755
--- a/vision_apps/platform/am62a/rtos/gen_linker_mem_map.py
+++ b/vision_apps/platform/am62a/rtos/gen_linker_mem_map.py
@@ -218,27 +218,27 @@ ddr_viss_config_heap_size = 4*MB;
carveout_size += ddr_viss_config_heap_size
mcu_r5f_ddr_local_heap_addr = ddr_viss_config_heap_addr + ddr_viss_config_heap_size;
-mcu_r5f_ddr_local_heap_size = 16*MB;
+mcu_r5f_ddr_local_heap_size = 4*MB;
carveout_size += mcu_r5f_ddr_local_heap_size
dm_r5f_ddr_local_heap_addr = mcu_r5f_ddr_local_heap_addr + mcu_r5f_ddr_local_heap_size;
-dm_r5f_ddr_local_heap_size = 16*MB;
+dm_r5f_ddr_local_heap_size = 4*MB;
carveout_size += dm_r5f_ddr_local_heap_size
c7x_1_ddr_local_heap_non_cacheable_addr = dm_r5f_ddr_local_heap_addr + dm_r5f_ddr_local_heap_size;
-c7x_1_ddr_local_heap_non_cacheable_size = 16*MB;
+c7x_1_ddr_local_heap_non_cacheable_size = 4*MB;
carveout_size += c7x_1_ddr_local_heap_non_cacheable_size
c7x_1_ddr_scratch_non_cacheable_addr = c7x_1_ddr_local_heap_non_cacheable_addr + c7x_1_ddr_local_heap_non_cacheable_size;
-c7x_1_ddr_scratch_non_cacheable_size = 16*MB;
+c7x_1_ddr_scratch_non_cacheable_size = 4*MB;
carveout_size += c7x_1_ddr_scratch_non_cacheable_size
c7x_1_ddr_local_heap_addr = c7x_1_ddr_scratch_non_cacheable_addr + c7x_1_ddr_scratch_non_cacheable_size;
-c7x_1_ddr_local_heap_size = 112*MB;
+c7x_1_ddr_local_heap_size = 28*MB;
carveout_size += c7x_1_ddr_local_heap_size
c7x_1_ddr_scratch_addr = c7x_1_ddr_local_heap_addr + c7x_1_ddr_local_heap_size;
-c7x_1_ddr_scratch_size = 112*MB;
+c7x_1_ddr_scratch_size = 28*MB;
carveout_size += c7x_1_ddr_scratch_size
assert carveout_size <= ddr_mem_size_2arch/arm64/boot/dts/ti/k3-am62a7-sk-edgeai.dtso kernel device tree file change
// SPDX-License-Identifier: GPL-2.0
/*
* DT overlay for AM62A edgeAI carveouts
* Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
/plugin/;
&{/reserved-memory} {
#address-cells = <2>;
#size-cells = <2>;
ranges;
edgeai_memory_region: edgeai-dma-memory@a1000000 {
compatible = "shared-dma-pool";
reg = <0x00 0xa1000000 0x00 0x02000000>;
no-map;
};
edgeai_shared_region: edgeai_shared-memories {
compatible = "dma-heap-carveout";
reg = <0x00 0xa3000000 0x00 0x0ac00000>;
};
edgeai_core_heaps: edgeai-core-heap-memory@adc00000 {
compatible = "shared-dma-pool";
reg = <0x00 0xadc00000 0x00 0x4c00000>;
no-map;
};
};Note: only "edgeai_core_heaps" node change in above dts.
Also, We are keeping the CMA memory to 200MB only. As per my understanding, FIRMWARE BUILDER SDK changes need not to be done for CMA memory.
After doing memory map changes,we have followed all the step mentioned in the FIRMWARE BUILDER document and generated the vx_app_rtos_linux_mcu1_0_strip.out (DMR5 firmware) and vx_app_rtos_linux_c7x_1.out (c7x firmware). Further, we have used vx_app_rtos_linux_mcu1_0_strip.out (DMR5 firmware) firmware to generate our tispl.bin binary.
After doing all the changes, we have booted the board with new tispl.bin (new vx_app_rtos_linux_mcu1_0_strip.out (DMR5 firmware) used ti generate the tispl.bin) and vx_app_rtos_linux_c7x_1.out (c7x firmware).
After that, we have run the "TIOVX conformance test" to verify the memory related changes are done properly or not. We used psdk_rtos_ti_data_set_11_01_00.tar.gz and psdk_rtos_ti_data_set_11_01_00_am62a.tar.gz data set for conformance test as mentioned in the FIRMWARE BUILDER document. But the conformance test is failing(providing the segmentation fault) on our device. Below are the last logs from the conformance test.
TIOVX-Conformance-Test-1GB-DDR-Result.txt
But "TIDL conformance test" is passing for our board.
what could be wrong here for "TIOVX conformance test"? Let us know any other information is required.
Regards,
Jay
