Part Number: TMS320C6655
Hi TI Experts,
Customer is working on C6655, and using the SRIO to connect C6655 with FPGA.
Customer is currently debugging the communication between our DSP and the FPGA. After initialization, there is a possibility of lane misalignment, requiring synchronized multi-retraining on both sides.
Customer wants to know what reset methods are available for the SRIO module on the C6655 side? (Re-initializing the entire module may take a long time, making it difficult to control synchronization between both sides)
Thanks,
Kevin

