Problems on running C6accel app with VPSS firmware and driver loaded

This for the codec engine examples to run with video firmware running. For c6accel, modifying

$(C6ACCEL_INSTALL_DIR)/soc/packages/ti/c6accel_unitservers/TI816X/serverplatforms.xs

might help. I made these changes(shown in red text below) to get updated memory map for TI814x 1GB (not the TI816x) platform in

$(CODEC_ENGINE_PATH)/examples/ti/sdo/ce/examples/servers/all_codecs/package.bld,

per the wiki, thus:

/*
 *  ======== package.bld ========
 */

var Build = xdc.useModule('xdc.bld.BuildEnvironment');
var Pkg = xdc.useModule('xdc.bld.PackageContents');

var serverBaseName = "all";

/* when constructing a release, release everything */
//Pkg.attrs.exportExe = true;
Pkg.otherFiles = [
    "main.c", "setid.c", "all_mc.cfg", "all_syslink.cfg", "heaps.cfg",
    "link.cmd", "package.bld", "_config.bld", "makefile",
    "ti_platforms_evm3530.cfg", "ti_platforms_evm6472.cfg",
    "ti_platforms_evmDM8148.cfg",
    "ti_platforms_evmTI814X.cfg", "ti_platforms_evmTI816X.cfg",
    "serverplatforms.xs", "package/info"
    ];

var DM8148_DSP_ExtMemMap = {
 DDR3_HOST: {
 comment: "DDR3 Memory reserved for use by the A8",
 name: "DDR3_HOST",
 base: 0x80000000,
 len: 0x16c00000 /* 364 MB */
 },
 DDR3_DSP: {
 comment: "DDR3 Memory reserved for use by the C674",
 name: "DDR3_DSP",
 base: 0x96C00000,
 len: 0x1400000 /* 20 MB */
 },
 DDRALGHEAP: {
 comment: "DDR3 Memory reserved for use by algorithms on the C674",
 name: "DDRALGHEAP",
 base: 0x98000000,
 len: 0x1400000 /* 20 MB */
 },
 DDR3_SR1: {
 comment: "DDR3 Memory reserved for use by SharedRegion 1 (IPC)",
 name: "DDR3_SR1",
 base: 0x9A100000,
 len: 0x00100000 /* 1 MB */
 },
 DDR3_SR0: {
 comment: "DDR3 Memory reserved for use by SharedRegion 0 (SYSLINK)",
 name: "DDR3_SR0",
 base: 0x9F700000,
 len: 0x00200000 /* 2 MB */
 },

};

xdc.useModule('xdc.bld.BuildEnvironment');
// set'theProf' to 'debug' for faster builds (with lower performance)
var theProf = 'debug';//'whole_program_debug';

/* bin/ is a generated directory that 'xdc clean' should remove */
Pkg.generatedFiles.$add("bin/");

/*
 * When using this package with the CE examples build, xdcpaths.mak can be
 * used to determine which PROGRAMS to build for (e.g. APP_LOCAL or APP_CLIENT).
 *
 * If PROGRAMS is set via the XDCARGS, we respect that, and only build what's
 * requested.  Else, we build everything we can.
 */
var programs = undefined;
for (x = 0; x < arguments.length; x++) {
    if (arguments[x].match(/^PROGRAMS=/)) {
        programs = arguments[x].split("=")[1];
//        print("programs:  " + programs);
    }
}

for (var i = 0; i < Build.targets.length; i++) {

    if ((programs != undefined) && (!programs.match(/DSP_SERVER/))) {
        break;
    }

    var targ = Build.targets[i];

    /* only build for BIOS-based targets */
    if (targ.os == undefined) {

        /* No A8 Server yet */
        if (targ.isa == "v7A") {
            continue;
        }

//        print("building for target " + targ + " ...");

        /* Platforms were added to targ.platforms[] in config.bld */
        for (var j = 0; j < targ.platforms.length; j++) {
            var platform = targ.platforms[j];

//            print("  platform:  " + platform);

            var platInst = Build.usePlatform(platform);
            var platMod = platInst.$module;

            if (platform.match(/simTesla/) || platform.match(/sdp4430/)) {
//                print("   skipping unsupported platform");
                continue;
            }

            if (platform.match(/evm6472|evm6474|6608|6616|6670|6678/)) {
                /* homogeneous multicore, IPC-based Server */
                addExe(targ, platform, "all_mc");
            }
            else {

 /* platform instances used by this package */
 Build.platformTable["ti.platforms.evmTI814X:DSP"] = {
 externalMemoryMap: [
 [ "DDR3_DSP", DM8148_DSP_ExtMemMap.DDR3_DSP ],
 [ "DDRALGHEAP", DM8148_DSP_ExtMemMap.DDRALGHEAP ],
 [ "DDR3_SR1", DM8148_DSP_ExtMemMap.DDR3_SR1 ],
 [ "DDR3_SR0", DM8148_DSP_ExtMemMap.DDR3_SR0 ]
 ],
 codeMemory: "DDR3_DSP",
 dataMemory: "DDR3_DSP",
 stackMemory: "DDR3_DSP"
 };
                /* heterogeneous multicore, syslink-based Server */
                addExe(targ, platform, "all_syslink");
            }
        }
    }
}

/*
 *  ======== addExe ========
 */
function addExe(targ, platform, cfg)
{
    var lld = false; /* unfortunately, assume lld isn't supported */

    /* if on a C64, cache is enabled, and buffer alignment is 128 */
    var compileOpts = targ.suffix.match("64") ?
        "-DBUFALIGN=128 -DCACHE_ENABLED" : "";

    /* Create the list of source files to build. */
    var srcs = ["main.c"];

    if (platform.match(/6472|6474|6616|6608|6670|6678/)) {
        srcs = ["main.c", "setid.c"];
        if (targ.$package == 'ti.targets') {
            lld = true;
        }
    }

    // name = bin/platform/name.x+suffix
    var serverCoreSuffix = platform.match(/:.*$/);
    if (serverCoreSuffix != null) {
        serverCoreSuffix = serverCoreSuffix[0].replace(/\:/g, "_");
    }
    else {
        serverCoreSuffix = "";
    }

    var platformBaseName = platform.replace(/(\w+)\:.*$/, "$1").replace(/\./g, "_");
    var name = "bin/" +
        platformBaseName + '/' + serverBaseName + serverCoreSuffix;
print("exe name = '" + name + "'");

    Pkg.addExecutable(name, targ, platform, {
        copts: compileOpts,
        profile: theProf,
        cfgScript: cfg + ".cfg",
        cfgArgs: "{ platform: \"" + platform + "\" }",
        cfgArgs: "{ lld : " + lld  + "}",
        lopts: "-l link.cmd"
    }).addObjects(srcs);
}

/*
 *  @(#) ti.sdo.ce.examples.servers.all_codecs; 1, 0, 0,261; 12-2-2011 14:52:49; /db/atree/library/trees/ce/ce-s25x/src/ xlibrary

 */

The changes were made per this link: http://processors.wiki.ti.com/index.php/Codec_Engine_Server_Integrator_User's_Guide#Platform_Memory_Map_Configuration_.28BIOS6.29

cmem load script must be updated per this link:

http:/processors.wiki.ti.com/index.php/HOWTO_Change_the_Linux_Kernel_Start_Address#Updating_CMEM_Memory_Region"> http:/processors.wiki.ti.com/index.php/HOWTO_Change_the_Linux_Kernel_Start_Address#Updating_CMEM_Memory_Region">http://processors.wiki.ti.com/index.php/HOWTO_Change_the_Linux_Kernel_Start_Address#Updating_CMEM_Memory_Region

In my case for  1GB TI814x EVM with 5.03 EZSDK cmem's  phys_start=0x96C00000 phys_end=0x97ffffff

I am still working on this. Will let you know if this works. 

RV

RV,

Don`t you think your CMEM and DDR3_DSP regions are overlapping. I think you need to change your DDR3_DSP configuration to start at 0x99500000 as specified by the Memory map on that wiki.

Regards,

Rahul