Part Number: TDA4VM-Q1
Hello,
I need to change the UART Debug Console to main_uart1 on a J721e based board.
The serial interface is working using minicom between the board and the host (PC).
I found previous discussion about this but it doesn't work.
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1579478/tda4vm-change-the-uart-debug-console
In u-boot, I added some properties in the u-boot devicetree:
+&main_uart1 {
+ bootph-all;
+ /* Shared with ATF on this platform */
+ power-domains = <&k3_pds 278 TI_SCI_PD_SHARED>;
+};
+&main_uart1_pins_default {
+ bootph-all;
+};
I updated u-boot environment
+console=ttyS3,115200n8
+args_all=setenv optargs earlycon=ns16550a,mmio32,0x02810000
I updated optee-os and ATF package to use main_uart1 (from meta-ti)
+TFA_K3_USART = "0x1"
+OPTEE_K3_USART = "0x1"
As, is the main_uart0 is still used but I start to see optee log in the main_uart1.
So far so good, I update the stdout-path property:
chosen {
+ stdout-path = "serial3:115200n8";
};
With this change, nothing boot.
I can only see some characters from the wkup_uart port
Do I need to update arch/arm/mach-k3/r5/j721e/clk-data.c too ?
I tried (without success):
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 48000000),
+ DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"),
+ DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
Is any issue related to the DM firmware that may have be built for the J721e evm using main_uart0 by default?
Best regards,
Romain
