How to have a shared memory access in c6474?

Shoba.G,

Please see the E2E thread How to synchronize the three cores of C6474 without DSP/BIOS. In spite of the name, there is an example project attached to one of my posts on that thread named C6474_Edma_IPC_BIOS.zip. That project shows sending messages from one core to the next and transferring data from one core to the next with some processing going on in the middle. This may help you understand methods that can be used.

But basically, the answer to your question is that you just send another IPC interrupt from core1 or core2 to core0.

Regards,
RandyP

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Hi RandyP

Thanks for the immediate response.  I had already gone through those links.  As I am not supposed to use DSP/Bios or CSL (need to program the DSP hard core) I am not finding it very useful.  I tried IPC interrupt from core1 and core2 to core0.  But don't know why it is not working.  Then tried using a shared memory using aliased addressing as specified in multicore programming guide (also mentioned in one of your earlier answer).  But the value which core1 and core2 are updating is not reflected in core0.  Is it because of cache coherency?  How to go about it? kindly guide me..

Regards,

Shoba.G

Shoba.G,

It is always surprising to me when people say the do not want to use DSP/BIOS or CSL or PSP (Platform Support Package). These are the tools that we take the time to write and debug so that you do not have to write and debug the same thing on your own. There are some reasonable discussions on this topic in this thread and in that thread.

My recommendation is to use CSL to get the project working. Then read through the source code of the CSL and reduce it to whatever method you prefer to use. All of the CSL source code is available.

You were able to get IPC working from Core0 to Core1, so you should be able to get it working from Core1 to Core0. Your resource is the documentation in ht e various User's Guides, Reference Guides, and the datasheet.

Find the documents on cache operation and the cache coherency commands and try using them. The CCSv5 Memory Browser has highlights that show when data is stored in cache, and check boxes to clear so you can see what is outside of the cache.

In the Training section of TI.com, there is a training video set for the C6474. It may be helpful for you to review all of the modules. You can find the complete video set here.

Regards,
RandyP

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Dear RandyP,

Thanks for the reply,  sorry for the frustration.  What can I do?  The requirement is to do hard-core programming.

 The requirement is this.  Core0 runs a timer and in the ISR of the timer interrupt , IPC interrupt is given to core1 and core2.  IPC ISR of core1 and core2 does some calculations and has to inform the core0 that they have finished their job.  Timer interrupt and IPC interrupts are routed though interrupt channel 5 by using vector.asm and INTMUX1.

When tried IPC interrupt from core1 and core2 to core0 back for intimation, I tried routing it in a different channel say channel 6.  But this is not working.

But I went as per your advice and checked the example codes of cache using CSL.  So accordingly set the corresponding cache registers for using a DDR2 memory location as a flag which will be set by core1 and core2 after completing their jobs. With this cache coherency is maintained between core1's L2 and DDR2 and the same for core2's.  This is also reflected in the  memory window (DDR) of core0 when I halt the program.  But while running   when core0  checks for the flag it always gets previous value not the updated one by core1 and core2.  Should there be a EDMA transfer intiated after setting the flag by core1 and core2.

I didn't understand the term core-agnostic which is mentioned in Multi-core programming guide.

May be I am troubling more with my stupid doubts, but I need your guidance.

Regards,
Shoba.G
 

Shoba.G,

Please understand that someone spent considerable resources to write hard-core programming and then to package that into APIs accessible through CSL and/or SYS/BIOS. Whoever did that documented the APIs and offers those as libraries that will allow you to get the job done in the quickest and easiest way possible.

It is very practical for TI to offer support for your use of those tested APIs, with examples and documents and answers here on the forum.

If you have an artificial requirement to do hard-core programming, which requires a lot of time and effort and learning on your part, then you will also require a lot of time and effort from consultants to answer your questions.

If you do not wish to hire experienced consultants to do this work for you, then my recommendation is to get it working with the methods we support, CSL and SYS/BIOS. Then use your success there to back it down to meet your hard-core requirements. As you make changes or write functions differently, you can compare register settings to those from the working method to those of the new method you are trying to develop.

shobha gopal said:

So accordingly set the corresponding cache registers for using a DDR2 memory location as a flag which will be set by core1 and core2 after completing their jobs. With this cache coherency is maintained between core1's L2 and DDR2 and the same for core2's.  This is also reflected in the  memory window (DDR) of core0 when I halt the program.  But while running   when core0  checks for the flag it always gets previous value not the updated one by core1 and core2.

"set the corresponding cache registers" does not explain "cache coherency is maintained". And "reflected in the memory window of core0" and "core0 ... always gets previous value" are opposites and should not both be true. My guess is that coherency is not maintained with core0.

"core-agnostic" could mean different things depending on context, but generally it means it does not matter which core is used.

Regards,
RandyP