DM8148: Clock Management for AV Synchronization

More details from customer below –

Attached block diagram illustrating 2 cases we are looking at below.

Based on my design requirement, I have two possible choices:

1.     Fixed 20MHz input to DEVOSC. The 20MHz is the base clock for most of the internal PLLs to generate the necessary interface clocks. The 27MHz video reference can be derived from 20MHz using one of the internal Video DPLLJ (Low Jitter PLL with pre-divide with Fractional Multiplier), say DPLL_VIDEO0. Software can control the frequency adjustment of DPLL_VIDEO0’s (DCXO) 27MHz, as mentioned in Section 2.3.7 of TRM:

“The device has options for DCXO/VCXO type feature to adjust video frequency on the fly: Use an off-chip VCXO on AUXOSC_ (can feed clock to AUXOSC XI pad and run AUXOSC in bypass) (controlled by VIC within TPPSS). This provides the most smooth, low jitter solution. In each case, software will control the frequency adjustment (via manipulation of off-chip VCXO through TPPSS VIC pin or other means).”

The DPLL_VIDEO0’s (DCXO) output can then be fed as input to an Audio PLL, Audio_PLL_Clk4 (DPLLJ), which supports PLL dividers are mentioned in Table 2-24. The question  is ‘are the Audio PLL internal dividers capable of generating audio clock frequencies (24.576MHz and 22.5792MHz) from DPLL_VIDEO0’s 27MHz?’. If it could be done, then I have a solution, despite higher jitter due to DCXO. Furthermore, for better jitter performance, I could then use an external 27MHz VCXO connected to AUXOSC instead of DPLL_VIDEO0. As you can see, this case depends on the internal Audio PLL to generate the required audio frequencies from 27MHz. We need more information on the software control of the DCXO .

2.     Alternatively, the frequency adjusted (software controlled DCXO) DPLL_VIDEO0’s 27MHz output is sent out on the CLKOUT pin, Section 2.3.11 of TRM. The CLKOUT can be fed to an ‘External Audio PLL’ which generates the necessary audio frequencies. The output of the ‘External Audio PLL’ can then be input to AUXOSC, which is internally routed to the AUDIO Interfaces. This solution depends on the jitter on CLKOUT pin, which in turn is dependent on the DCXO.

It would have been ideal to use external 27MHz VCXO and external Audio PLL, but there are only 2 clock inputs on the DM8148, and 1 is reserved for 20MHz.

Regarding the audio frequencies, 24.576MHz and 22.5792MHz, used for 48KHz and 44.1KHz respectively, are the common sampling rates associated with video files.

I look forward to your inputs.

Thanks,

Prateek