Part Number: DRA821U-Q1
Other Parts Discussed in Thread: DRA821
Kernel panic not syncing Asynchronous SError Interrupt.txt
Hi there,
My custom board boots correctly most of time, but occasionally it failed booting with kernel panic messages. I attached the console output (probably missing the first couple of seconds at the beginning). The J7200 SDK version is v10.0.
Can you tell me what may cause this issue?
Thanks,
Charles
Hi Charles,
Allow us some time to reproduce this on EVM at our end as well,
Since the stack trace can look similar on Linux ,but reason for those can be quite different from custom board to EVM. We still would like to debug further on custom board as well.
To enable the TIFS traces apart from board config changes have we made changes to enable the wakeup UART as well? Can you share complete steps.
Also, TIFS does dump the traces in memory buffer as well , You can see if you are getting any traces their after connecting via jtag and dumping the memory
Ref:Trace Layer — TISCI User Guide
Regards
Diwakar
HI Charles,
Can you cross check the test steps which i performed is the same as yours.
We need to check in wakeup uart not in MCU uart. You will get two instance of UART when you connect to J43, we need to open first instance of it.
We dont need to change any DIP switch setting for UART on EVM.
Regards
Diwakar
Hi Diwakar,
I assume you mean the photo of EVM (see below). As for software image, you should be able to figure out from the UART log, correct?
Also, based on both trace and UART logs I provided, you should be able to start investigating the cause, correct? You may need to replicate the problem in order to validate your future solution, but not necessary for investigation of the root cause. Anyways, if you need me to do more tests, please let me know. We need the answer right away since our project is already behind the schedule. Thanks for your help.
Thanks,
Charles
Hi Charles,
I assume you mean the photo of EVM (see below). As for software image, you should be able to figure out from the UART log, correct?
That is correct i was looking for EVM image to compare with what i have, i see the EVM which i have has assy marked as differently then the EVM which you are having.
EVM Which i have:
Your board:
Also, based on both trace and UART logs I provided, you should be able to start investigating the cause, correct?
I looked in to the traces which you have shared on the EVM, it has three set of issues.
So from softwarer point of view the crash/stall is random and not reproducible at my end. I am trying to see if we can find similar version of board which you are having and see if we can replicate the issue.
Can you also try below changes in your custom board and see if issue re-appear
diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c index db0160c6e..0888fd241 100644 --- a/drivers/irqchip/irq-ti-sci-inta.c +++ b/drivers/irqchip/irq-ti-sci-inta.c @@ -155,11 +155,12 @@ static void ti_sci_inta_irq_handler(struct irq_desc *desc) vint_desc = irq_desc_get_handler_data(desc); domain = vint_desc->domain; inta = domain->host_data; - chained_irq_enter(irq_desc_get_chip(desc), desc); - val = readq_relaxed(inta->base + vint_desc->vint_id * 0x1000 + + val = readl_relaxed(inta->base + vint_desc->vint_id * 0x1000 + VINT_STATUS_MASKED_OFFSET); + val|= ((u64)readl_relaxed(inta->base + vint_desc->vint_id * 0x1000 + + VINT_STATUS_MASKED_OFFSET+4)<<32) ; for_each_set_bit(bit, &val, MAX_EVENTS_PER_VINT) generic_handle_domain_irq(domain, vint_desc->events[bit].hwirq);
Regards
Diwakar
The difference between Rev E8A and E8B is silicon revision only (as shown in the schematic change log)
