8148 EDMA completion interrupts problem

Ross Leppard

Hi,

I'm using the 8148 EVM board and am writing a simple UART driver using DMA. I currently set the UART into DMA for TX operations and configure the EDMA controller with a single PaRAM entry to do a fixed size transfer of ACNT = 1, BCNT = 50, CCNT = 1. In the OPT section of the PaRAM I have set the TCINTEN bit to 1 which I believe should then set a bit in the IPR that corresponds to the value I put into the TCC field on completion of the final transfer of the PaRAM, in this case after the 50th byte has been transferred.

The DMA transfer itself is working fine, I see the correct data coming out of the UART but when I look in the IPR no bits are set at all regardless of what TCC value I use?

I don't actually want an interrupt generated, I will be polling the IPR, so I have not set any bits in the IER but according to the TRM the bits should still be set in the IPR. I am running my code from the ARM core and using the global region to access the registers, no shadow regions are being used, so I am looking at offset 1068h for the IPR.

Is there anything else I need to set to enable the setting of the IPR bits on completion?

over 13 years ago

0 Sandeep R over 13 years ago

TI__Prodigy 550 points

Ross,

can you check the thread @ http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/t/7503.aspx#29570 & see if this helps fix your problem?

regards, Sandeep

0 Ross Leppard over 13 years ago in reply to Sandeep R

Prodigy 70 points

Thanks for the reply Sandeep, unfortunately that post dosn't seem to have anything to fix my problem.

My issue is of the second type mentioned in that post, I never see the IPR bit being set even after >1 second.

The PaRAM setting I am using are as follows: -

    Uart0_Tx_PaRam->Options         = 0x0011A000u;
    Uart0_Tx_PaRam->Source_Addr     = (uint32)&Write_String[0];
    Uart0_Tx_PaRam->A_Count         = 1;
    Uart0_Tx_PaRam->B_Count         = 10;
    Uart0_Tx_PaRam->Dest_Addr       = UartBaseAddress + THR_OFFSET;
    Uart0_Tx_PaRam->Src_BCNT_Index = 1;
    Uart0_Tx_PaRam->Dest_BCNT_Index = 0;
    Uart0_Tx_PaRam->Link_Addr       = 0xFFFF;
    Uart0_Tx_PaRam->BCNT_Reload     = 0;
    Uart0_Tx_PaRam->Src_CCNT_Index = 0;
    Uart0_Tx_PaRam->Dest_CCNT_Index = 0;
    Uart0_Tx_PaRam->C_Count         = 1;
    Uart0_Tx_PaRam->Reserved        = 0;

Which other register settings could be related to the setting of IPR bits on completion?

Thanks,

Ross

0 Sandeep R over 13 years ago in reply to Ross Leppard

TI__Prodigy 550 points

Ross,

From your configuration you are using a TCC = 26; Right?

Section 8.8 of the TRM @ http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=sprugz8a&fileType=pdf explains the edma setup.

Also can you share the register value of IESR (at offset 0x1060)?

Regards, Sandeep

0 Ross Leppard over 13 years ago in reply to Sandeep R

Prodigy 70 points

Sandeep,

Yes I have set the TCC to 26 to match the event number of the UART0 Tx events but I have also tried other values with no success.

I have not written anything to the IESR register so the IER is still at its default values (all 0) as I don't want an actual interrupt to be generated, just the completion bit set.

The TRM is the document I have been using so far, especially the examples in section 8.5.4.1.

Thanks,

Ross

0 Sandeep R over 13 years ago in reply to Ross Leppard

TI__Prodigy 550 points

Ross,

IESR[TCC] needs to be set to '1' to have IER[TCC] set to '1' & in turn have the IPR[TCC] set to '1' on the completion of edma transfer. Hope this helps.

Regards, Sandeep

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8148 EDMA completion interrupts problem