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CLOCKING FOR TMS320C6678 / USING EVM TMDXEVM6678L AS REFERENCE

Ran Feldman
Intellectual 780 points

Hello,

The   has an evm P/N: TMDXEVM6678L

For the Clocking on this evm:

Our customer would like to omit the generator components for 100MHz, 66MHz and 312.5MHz used on the TMDXEVM6678L.

They want to provide the 100MHz and 66MHz clocks directly from the FPGA. They would also like to omit the 312.5MHz clock, as it imposes difficulty in implementation.

Please clarify if other frequency can be used and fed to SRIOSGMIICLK.

if they are not going  to use SRIO functionality in their platform, only SGMII. Table 7-26 (Main PLL Controller/SRIO/HyperLink/PCIe Clock Input Timing Requirements) in the DSP data sheet specifies SRIOSMGMIICLK cycle time as 3.2 to 6.4 ns, does this mean that the allowed frequencies are 312.5 and 625MHz?

Rephrasing the same question: what is the minimum clock frequency required to operate SGMII interface on the network co-processor?

Thanks,

Ran

  • 0
    TI__Intellectual 1880 points

    Ran,

    I cannot directly comment on the 100 MHz and 66MHz clocks, but I can provide information for the SRIOSGMIICLK. However, before commenting, you may find it helpful to consult the Keystone Hardware Design Guide (SPRABI2A), which provides a lot of details on the clocking requirements. Figure 4 in this document shows the acceptable reference clock frequencies for C66x devices.

    The SRIOSGMIICLK input clock  can operate in the 156.25 MHz to 312.5 MHz operating range. The timing numbers that you quoted in the data sheet are correct, however, the frequencies that you have mentioned are incorrect. The fastest period supported is 3.2 ns, which is 312.5 MHz. The slowest period supported is 6.4 ns, which is 156.25 MHz.

  • 0 in reply to Derek Brown
    TI__Mastermind 46460 points

    Ran,

    Derek's answer is not quite right.  The C6678 SERDES clock reference inputs are only characterized at discrete frequencies.  They do not operate over a range of input frequencies.  The SRIOSGMIICLK, MCMCLK and PCIECLK inputs support the nominal frequencies 156.25MHz, 250MHz and 312.5MHz.  PCIECLK also supports the nominal frequency 100MHz.  Other frequencies are not supported.  Additionally, these must be very low-jitter clock sources so that the SERDES interfaces can operate at the expected BER performance levels.

    The C6678 Data Manual does not capture this correctly and needs to be updated.  The KeyStone Hardware Design Guide has part of the information and a new release with it revised is coming out soon.  The attached PDF contains the discussion that will be placed into the Hardware Design Guide.  7573.RefClk jitter v1.pdf

    Tom

     

  • 0 in reply to Tom Johnson 16214
    TI__Mastermind 46460 points

    Ran,

    Note that the CORECLK, DDRCLK and PASSCLK inputs do accept any frequency between 40MHz and 312.5MHz.  The KeyStone Hardware Design Guide does correctly list the jitter requirements for these clock inputs.  You must make sure the jitter requirements are met.  Also note that the power/clock/reset sequencing requirements for the clocks must also be observed.  This is shown in the power sequencing section of the Data Manual.

    Tom