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Problem of EDMA3 in C6455

Pei Luo
Prodigy 80 points

I am using EDMA3 in C6455 DSP, and there is a problem of the data transferring.

 

Here is the phenomenon, I use EDMA3 to read data from FIFO in FPGA Virtex5 through EMIFA CE4, and the first 4 bytes are lost while the last 4 bytes repeated twice. For example, the 1K bytes data should be 0x0000 – 0x0400 (1 - 1024), but the result is 0x0004 – 0x0400 and 0x03FD – 0x0400 (1021 - 1024) repeated twice.

 

 

Here is my configuration of EMIFA:

         EMIFA_CONFIGREG_STAT &= ~(0x80000000) ;       //config emifa work in little endian mode

EMIFA_CONFIGREG_CE4CFG |= 0x8000030b;

 

The following is my configuration of EDMA3:

         pEDMA3CC_PaRAM->OPT = 0x00100201; //TCINTEN=1;TCC=0;SYNCDIM=1;

         pEDMA3CC_PaRAM->SRC = EMIFA_CE4_BASE_ADDR;

         pEDMA3CC_PaRAM->BCNT_ACNT = 0x00010800; //ACNT=1024;BCNT=1;

         pEDMA3CC_PaRAM->DST = FPGA_DATA_PING;

         pEDMA3CC_PaRAM->DSTBIDX_SRCBIDX = 0x00000000;

         pEDMA3CC_PaRAM->BCNTRLD_LINK = 0x00804060; //LINK=4060, PaRMA SET 3

         pEDMA3CC_PaRAM->DSTCIDX_SRCCIDX = 0x0;

         pEDMA3CC_PaRAM->RSVD_CCNT = 0x00000001;

 

The read latency of Xilinx FIFO is one clock cycle. Can anyone help to firgure out the problem?

  • 0
    TI__Guru* 84110 points

    Pei Luo,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    You did not say what address pEDMA3CC_PaRAM is pointing to or what is in PaRAM Set 3, so there could be other problems there.

    Pei Luo said:
    pEDMA3CC_PaRAM->OPT = 0x00100201; //TCINTEN=1;TCC=0;SYNCDIM=1;

    Your comment says SYNCDIM=1 but it is actually 0. Did you set the wrong bit?

    Do not use SAM=1 or DAM=1. This is only to be used when a peripheral supports it, and I do not believe anything in the C6455 supports it. Please see the Note is section 2.3.8 of the EDMA3 User's Guide.

    Clearing SAM to 0 will probably fix your problem.

    Pei Luo said:
    pEDMA3CC_PaRAM->BCNT_ACNT = 0x00010800; //ACNT=1024;BCNT=1;

    Your comment says ACNT=1024 but the value used is 2048 Bytes.

    Pei Luo said:
    pEDMA3CC_PaRAM->BCNTRLD_LINK = 0x00804060; //LINK=4060, PaRMA SET 3

    I am curious, why did you set BCNTRL=0x0080? It is not used in this case, so it does not matter.

    Regards,
    RandyP

     

    If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

  • 0 in reply to RandyP
    Prodigy 80 points

    Thank you for your reply, I checked my design and found I pasted the wrong file last time, sorry for it.

    And the problem still remains after I changed my design according to your suggestion.

    I use CE4 area to read the FIFO in Xilinx Virtex5 FPGA and  I configure the register as following:

     EMIFA_CONFIGREG_CE4CFG |= 0x80000307;//0x80000307;

     

    I use PingPong Buffer and EDMA3 to read the data with the following configuration:

     pEDMA3CC_PaRAM = EDMA3CC_PaRAM1;
     pEDMA3CC_PaRAM->OPT = 0x00100000;                              //TCINTEN=1;TCC=0;SYNCDIM=0;
     pEDMA3CC_PaRAM->SRC = EMIFA_CE4_BASE_ADDR;
     pEDMA3CC_PaRAM->BCNT_ACNT = 0x00010800;              //ACNT=2048;BCNT=1;
     pEDMA3CC_PaRAM->DST = FPGA_DATA_PING;
     pEDMA3CC_PaRAM->DSTBIDX_SRCBIDX = 0x00000000;
     pEDMA3CC_PaRAM->BCNTRLD_LINK = 0x00014060;       //LINK=4060, PaRMA SET 3
     pEDMA3CC_PaRAM->DSTCIDX_SRCCIDX = 0x0;
     pEDMA3CC_PaRAM->RSVD_CCNT = 0x00000001;

    I set BCNT_ACNT = 0x00010800 because I need to read 1024*64bit data at one time, is that right?

    The error phenomenon remains as the images show above, can anyone firgure out the problem?

     

  • 0 in reply to Pei Luo
    TI__Guru* 84110 points

    What endianess are you using for the DSP?

    What is the display mode in the memory window? It appears to be 16-bit decimal.

    Do you expect the data to be backwards within each 64-bits?

    Why do you |= the value in CE4CFG? This could put the wrong value in there if you intended exactly that number to be placed there.

    Can you confirm on a scope or logic analyzer that the correct data is on the bus at the correct times? You must eliminate the FPGA as the source of this data error.

    What result will you see if you clear the data buffer to all 0's, run the EDMA transfer one time, then observe the memory buffer?

    Regards,
    RandyP