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C6455: problems in EDMA3 and the timing of EMIFA

Thomas Chen1
Prodigy 245 points

Hello!

I've got a strange problem of the edma and the timing of emifa. My project is about external GPIO4 interupt triggers the edma and the edma is transfering data from EMIFA CE2 to L2 sram. I use the chipscope of FPGA to see the signals of EMIFA and I found a really strange problem. The timing of EMIFA is affected by the data amout of edma. The data width of EMIFA is 64 bit and the clock of EMIFA is 100MHz. If the amount of edma transfer is less than 1024*64bit, the timing of EMIFA is correct. But if the amount is larger than 1024*64bits, the timing of EMIFA isn't correct, especially the signal of CE2 and OE. These two signals stop for one clock every 15 data, as the picture shows below.

Under normal conditions, the signal of CE2 and OE should be low until the total transfer is over, while the picture shows that these stop for one clock and continues to transfer.

The EMIFA is configured to 64 bit width and standard synchronous FIFO read. Here is the configuration of EMIFA.

CSL_EmifaSync  syncMem = { (Uint8)CSL_EMIFA_SYNCCFG_READBYTEEN_DEFAULT, \

                                                (Uint8)CSL_EMIFA_SYNCCFG_CHIPENEXT, \

                                                (Uint8)CSL_EMIFA_SYNCCFG_READEN, \

                                               (Uint8)CSL_EMIFA_SYNCCFG_WLTNCY_DEFAULT, \

                                               (Uint8)CSL_EMIFA_SYNCCFG_RLTNCY_1CYCLE, \

                                              (Uint8)CSL_EMIFA_SYNCCFG_SBSIZE_64BIT \

                                               };

 /* setting for synchronous type */

syncVal.ssel = 1;  //EMIFA_MEMTYPE_SYNC

syncVal.async = NULL;

syncVal.sync = &syncMem;

 

/* setup the hardware parameters */

hwSetup.asyncWait = NULL;

hwSetup.ceCfg[0] = &syncVal;    //CE2

hwSetup.ceCfg[1] = NULL;                //CE3

hwSetup.ceCfg[2] = NULL;           //CE4

hwSetup.ceCfg[3] = NULL;        //CE5   

 

The edma is configured to transfer 1024*64bit data in the interrupt service of GPIO4 int. Here is the configuration of the edma3.

    /* Setup the first param set */

    myParamSetup.option = CSL_EDMA3_OPT_MAKE (CSL_EDMA3_ITCCH_DIS, \

                                              CSL_EDMA3_TCCH_DIS, \

                                              CSL_EDMA3_ITCINT_DIS, \

                                              CSL_EDMA3_TCINT_EN,\

                                              0, CSL_EDMA3_TCC_NORMAL,\

                                              CSL_EDMA3_FIFOWIDTH_NONE, \

                                              CSL_EDMA3_STATIC_EN, \

                                              CSL_EDMA3_SYNC_AB, \

                                              CSL_EDMA3_ADDRMODE_INCR, \

                                              CSL_EDMA3_ADDRMODE_INCR 

                                             );          

    myParamSetup.srcAddr = EMIFA_CE2_BASE_ADDR;        

    myParamSetup.aCntbCnt =  CSL_EDMA3_CNT_MAKE(8,1024); 

    myParamSetup.dstAddr = L2_DATA_ADDR;       

    myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(8,8);    

    myParamSetup.linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);    

    myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);    

    myParamSetup.cCnt = 1;

 

If I change the number 1024 to any number between 1-1023, the timing of EMIFA is correct. If I set the number equal or larger than 1024, the timing of EMIFA isn’t correct.

I need your help, thanks for your reply!

  • 0
    TI__Guru* 84110 points

    A zoom in on two of the CE2 cycles might help to see what you have measured. The quality of our image insertion is not so good that I can see the picture in that detail. Sorry.

    A burst of 15 data reads is very strange, but even that would be less than the 1024 total CE2 reads that should have run. Is the picture for CNT=(8.1024) or CNT=(8,240)?

    My first thought was that the EDMA3 reaches a limit in terms of what it can optimize to. Please see Table 2-17 in the EDMA3 User's Guide.

    You can try setting ACNT=16 and BCNT=512 for the same desired results.

    How large of a transfer do you need to do?

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 245 points

    Hello! 

               Nice to see you, RandyP. In fact I'm wainting for you to answer my question, thanks for your warm reply!

              The EMIFA is configured to 64 bit width and standard synchronous FIFO read, the clock of EMIFA is 100MHz. So that the ACNT must be 8 to meet the 64bit data width and I want to transfer large amount of data in really fast speed. If I set the ACNT=8 and BCNT=1023 or less, the timing of EMIFA is correct and the data is right. When I set the ACNT=8 and BCNT=1024 or larger, the timing of EMIFA CE2 and OE stop for one clock  but the data and address are right. In order to reach the high speed, I want the signals of CE2 and OE act like the standard timing, which keeps low (valid) until the transfer is over.

               You remind me of the table which seem that the edma is optimized. So if I want to set ACNT=8 and BCNT=1024 or larger while signals of CE2 and OE act like the standard timing, what should I do? 

               Thanks for your reply and have a great weekend!

        

  • 0 in reply to Thomas Chen1
    TI__Guru* 84110 points

    Thomas,

    What you have observed is how the device will operate. You will be working within the capabilities of the device, which are called out in the datasheet and User Guides.

    Thomas Young said:
    You remind me of the table which seem that the edma is optimized. So if I want to set ACNT=8 and BCNT=1024 or larger while signals of CE2 and OE act like the standard timing, what should I do?

    With ACNT=8 and BCNT=1024, the table shows that the EDMA3 is not optimized.

    Please try the solution I offered above. Set ACNT=16 and BCNT=512. Observe the results and reply back with what you have found, please.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 245 points

    Hello!

    Thanks for your kind advice. I set the ACNT=16 and BCNT=512, the timing of EMIFA is correct as the picture shows.

    After that I change the BCNT to 1024 and 2048, the timing of EMIFA is correct as well. I think the problem has been solved.

    As the table 2-17 shows that if ACNT>DBS (64Bytes), the EDMA is not optimized. Can you explain why it works well?

        Thanks for your reply!

  • 0 in reply to Thomas Chen1
    TI__Guru* 84110 points

    Thomas

    Thomas Young said:

    As the table 2-17 shows that if ACNT>DBS (64Bytes), the EDMA is not optimized. Can you explain why it works well?

    The EDMA3 is designed to optimize transfers into a minimum set of Transfer Requests and a minimum number of internal bus operations when the criteria on the first line of Table 2-17 are met. If you need that process to be optimized, then you should use the criteria of the first line. In the other cases, the behavior is not specifically designed to be optimized in that way, but that is also not a guarantee that the external bus behavior is going to be less than optimal.

    I am glad you have a solution.

    On a thread to which I have already posted, I will automatically get an email unless I have unsubscribed. You do not need to forward each new post on an existing thread to me.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 245 points

    Hello!

    I’m sorry for notifying each new post on an existing thread to you.

    Here is another question I’m not quite sure. The goal of my project is transferring large amount of data from EMIFA to DDR2 in fast speed. The EMIFA is configured to 64 bit width while the data width of DDR2 is 32 bit, so that the data width isn’t matching and I can’t use the edma to directly transfer the data to the DDR2. So I transfer the data to the L2 SRAM and then I transfer the data from L2 SRAM to DDR2. As mentioned above, I set the ACNT=4 to fit for the 32bit data width of DDR2 and BCNT>1023, so the edma isn’t optimized and I’m worried about the timing of DDR2. Does the edma affect the timing of DDR2 again? Unlike the EMIFA, the timing of DDR2 can’t be caught by the FPGA. What should I do?

    Thanks for your patience and helpful advice!

  • 0 in reply to Thomas Chen1
    TI__Guru* 84110 points

    Thomas,

    Thomas Young said:
    The EMIFA is configured to 64 bit width while the data width of DDR2 is 32 bit, so that the data width isn’t matching and I can’t use the edma to directly transfer the data to the DDR2.

    Your conclusion is incorrect. The command optimization described in Section 2.12.1.1 and Table 2-17 means that using the following combinations to transfer 128 bytes will create the same end results on the two buses:

    ACNT,BCNT = 1,128
    ACNT,BCNT = 2.64
    ACNT,BCNT = 4,32
    ACNT,BCNT = 8,16
    ACNT,BCNT = 16,8
    ACNT,BCNT = 32,4
    ACNT,BCNT = 64,2
    ACNT,BCNT = 128,1

    As long as you keep ACNT and BCNT meeting the constraints of the first line of Table 2-17, you will get optimized commands issued by the EDMA3TC. Also keep in mind that the starting addresses for source and destination can affect the optimization of these commands for the first and last commands.

    You can use any of the above combinations transfer from EMIFA (64-bit) to DDR2 (32-bit). The TC will use the correct bus width.

    I would always use ACNT >= ALIGN where ALIGN is the minimum byte alignment for either the source or destination addresses. If both will be 32-bit or higher, use ACNT = 4 or greater, and so on. But any of the smaller values will still work as long as the command fragmentation is optimized.

    To be honest, I am not completely certain that the command optimization is the only reason for your EMFA transfers to be fragmented the way they were in your original post. Since you have a solution, there is no reason to worry about it, but I wanted to mention it just to be complete.

    If your total transfer requirement is larger than ACNT=64 * BCNT=1023, then you might consider self-chaining using the method described in my post on 3/2/2010 on the thread How does EDMA3 make a 3-dimension transfer?

    Regards,
    RandyP