DSP TMS320C6678 - Smart Reflex feature optional or mandatory

Dhamodharan,

Yes, it's mandatory to use Smart Reflex.  This has been posted many times before and is clear in the documentation.

You could use the recommended UCD9244/7242 combination for the core voltage. Please see also the HW design guidelines Section 5.9.

http://www.ti.com/litv/pdf/sprabi2

Best Regards,

Chad

Thanks Chad for your reply.

We have considered using UCD7242 with UCD9222 as in the DSP EVM. UCD7242 supports only max 10A current, but in our application it seems CVDD requires more than 12A current. So could please suggest the suitable available part?

Regards,

Dhamodharan

You can combine the UCD9222 with the UCD74111 for applications that require higher current.  The UCD74111 is a pin compatible follow-on to the UCD74110.  Both are single power supplies as opposed to the UCD7424 which is a dual supply.  For an example of the UCD9222 with the UCD74110 you can check the schematic for the TMDXEVM6670L on the Advantect website.  The C6670 EVM uses one half of the UCD9222 to control the UCD74110 for the core AVS supply and the other half to control a UCD74106 for the lower current fixed 1.0V supply.  The UCD74111 is currently in preview so check with your TI FAE for availability.

Isn't it "a" AVS? 

What can happen if one does not use SmartReflex? - Normally a power consumption increase and POH/Lifetime decrease like in typical x86.

Exactly what sprabi2b says: "In order to reduce device power, SmartReflex provides a feature that allows the core voltage to be optimized (scaled) based on the process corners of each device".

BTW - sprs691C says: "SmartReflex in the TMS320C6678 device is a feature" - so if it's a feature then it's a feature ;]

If it's not a feature so what happens when CVDD = CVDD1 = 0.95V : 1.05V [or even better]

The use of a SmartReflex supply for the core voltage is a requirement.  Each DSP is programmed with the required voltage level for that part.  If the core voltage is not maintained within the +/-5% of the requested voltage TI cannot guarantee the operation of the part. 

Thank you.

If you could please comment 3 of my statemets I would really appreciate. Those normally  apply to typical motherboards with x86.

1st - each DSP has it's own nominal CVDD it can be 0.9V but it can be 1.1V - due tue technological processes of some kind - so if you want to stay in SR class-0 you need to guess the nom/typ voltage or set it for every DSP - nominal of all nominals is 1.0V ;] - setting it to other values lead to : if less - to "blue screen" and data corruption ;], and setting it above nominal +5% to overheating or even burning.

2nd - it is still AVS/DVS so if you want a stable electronic/software system you really want SR class-3... otherwise preapare for the blue screen ;] or overheating [even if DSP is IDLE],

3rd - I have a board wit 4xC6678 and CVDD = CVDD1 = constant 1.0V +/- 2-5% - I've used TPS40132RHBT that gives circa 52A with only two coils [not with 8 coils like in UCDxxx solution] and my board is still working pretty good ;] - Heat Pipe seems to be doing a great job here :] - I guess I had have some luck with my DSP chip parts

Hi Bill,  TMDXEVM6670L is used  UCD9222 with the UCD74110,but can i use  UCD9222 with the UCD7242?

Now i use  UCD9222 with the UCD7242,but i have some problems:  When i connect cores in CCS V 5.3, the output  of UCD9222 is stable,  but if i connect cores with EVM6670.gel ,  the output  of UCD9222 is zero.

My UCD9222's  schematic is the same with TMDXEVM6670L,and the UCD7242's schematic is the same with TMDXEVM6678L~~~~

Hi Chen Jie,

The C6670 has a power consumption model on the webpage that you can use to determine the expected current requirements for you power supply design. The UCD7242 has a 10A limit per channel which may not be enough for your application.  You stated that the power supply is operating when when you connect code composer but fails when you run the EVM6670 gel. That gel will program the PLLs to a higher frequency and enable the DDR, increasing the current used by the part. If you are exceeding the current capability of the UCD7242 it may be shutting the power supply off to protect itself. You can monitor the output of the power supply using the Fusion software connected with the USB-to-GPIO pod to the PMBus. The Fusion Software will tell you if an over current flag is set or if the voltage dips below an acceptable level. 

Regards, Bill

Hi Bill, thanks very much for your reply.

I use C6670's  power consumption model,but i'm not familiar to the table, I refer to the C6678's setting to get the result as follows:

Bill,could you help me to analyze the table,whether 10A is enough for my design? 

what's more, I use Fusion Software to monitor  the voltage and current, some of my setting is as follows:

I wanna know the parameters  Iout Cal Gain and Iout Cal Offset  affect the real output current of  9222? Or just affect the display current of the software??

(If I set  the  Iout Cal Gain=100, the current display is about 4A and power down near 6A;  However, if  Iout Cal Gain=100,the current is 8A, and  power down near 10A )

The following picture shows the current ,power and voltage after loading fpga codes,but without connect cores in CCS; I'm puzzling why the current is so large even without connecting cores? If I don't load fpga codes,the current is about 6A.

Hi Chen Jie, 

Based the image of the power consumption model you've attached 10A is not enough for your design. The CVDD column defines the necessary current for the CVDD voltage rail. You're spreadsheet displays 11.119A in baseline current and 1.928A of active current for a total requirement of 13.048A. The baseline current is normal current draw due to leakage and other baseline activities.  This current draw should be present regardless of the activity of the cores. The active current is additional current that will be present when the cores are operating at the level you have specified in the model. I am not sure what you mean by loading fpga codes but it is not unusual to see current levels of 8 amps or higher before the devices is actively in use. 

The Fusion software uses the current monitoring capability of the UCD9222 and the UCD7242 to generate the information shown on the monitoring page. This information is only accurate if the software has been configured for the components used in your design. The details of how the current monitoring is achieved are described in the data manuals for the UCD components. The calibration settings in the Fusion software allow you to tune the outputs for your design to get more accurate readings. They do not effect the amount of current provided by the UCD7242 power stage, only how it is displayed. If you do not have the proper information for the components in your design and the proper calibration values loaded into Fusion the current measurements displayed will not be accurate. Note that these measurements are also used to determine the overcurrent state so it's important to get the settings correct. You should contact the power supply group supporting the UCD components if you have more questions setting up the current measurements. 

Regards, Bill

Hi Bill, thanks for your  reply.

I solve my problem using a fixed power whose limit  is 22A to CVDD.  The C6670 can work normally with loading .GEL file. What i'm in trouble is that the DDR Initialization failed using  the  .GEL  in ti\ccsv5\ccs_base\emulation\boards\evmc6670l\gel. My DDR design refers to  TMDXEVM6670L,so the PLL parameter should be  the same with evm's gel.  Bill, could give me some suggestions to solve this problem?   Thanks a lot ~ 

Hi Chen Jie,

The DDR3 initialization if the GEL file for the EVM is based on the EVM DDR3 layout. You will have to create initialization values that match your layout.  There are a number of good posts on the forum concerning this subject. Check the following post to get started.

http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/245304.aspx

Regards, Bill