Noticing in the SpO2 MDK there is a TIM0_IER register that isn't defined in the TMS320C5515 documentation. Is that real? Or is there processor difference that maybe I am not grasping.
#define CPU_TIM0_CTRL ((ioport volatile unsigned*)0x1810)
#define CPU_TIM0_PLWR ((ioport volatile unsigned*)0x1812)
#define CPU_TIM0_PHWR ((ioport volatile unsigned*)0x1813)
#define CPU_TIM0_CLWR ((ioport volatile unsigned*)0x1814)
#define CPU_TIM0_CHWR ((ioport volatile unsigned*)0x1815)
#define CPU_TIM0_IER ((ioport volatile unsigned*)0x1816)
