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What is the hardware and software breakpoint?

Other Parts Discussed in Thread: TMS320C6678

Hi,

There is a thread on multicore DSP mentioned hardware breakpoint. I do not know the difference of hardware and software breakpoint. Could you explain it to me?

Second, there are two version C6472 EVM. One has a fast emulation (XDS560) while the other is slower(XDS100). I see one capability of XDS560 is trace. What does that mean? It is hardare step though a line? Could someone explain it in detail to me?

 

Thanks again.

  • Robert,

    If you are just curious, go to the TI Wiki Pages and search on "hardware breakpoint" (no quotes). You will quickly find several interesting articles. If you are serious about learning and using them, install CCSv5 (using the simulator is free) and go to the Help->Search box to search on "hardware breakpoint" (no quotes); more interesting excerpts from the built-in documentation. Those resources will explain it better than I can.

    If you are on a super tight budget, stay with the XDS100 version of the EVM. If you can afford an extra $250 or so for a $1500 emulation value, you will have a much faster emulation experience in terms of download speed and responsiveness. Trace is just a nicety that you will not use until you have a big and complex multi-core application running that has a very hard-to-find bug in it - trace will let you see what is happening and greater observability is a big help with debugging a big and complex application on a complex and powerful multi-core device.

    If you are just starting to look at the multi-core C6472, you may want to consider the TMS320C6678 as a newer alternative. You may have some good reasons for using the very capable C6472, but I just wanted to put the suggestion out there for you.

    Regards,
    RandyP

  • Thank you very much. Your answer is very helpful. In fact, I am not strictly stick to C6472. C6678 is really a better alternative to us. Its capability is amazing!

  • Robert,

    With the C6678, you also have the added flexibility to scale down to 4 cores or 2 cores in a pin-compatible device to save cost if you do not need all 8 cores. I think that 4 1.0 GHz C66x cores will be very comparable to 6 C64x+ cores in the C6472. And if you are doing much floating point, then only 2 C66x cores could do what you need.

    Of course, most software engineers will gladly fill the available MIPS from 8 cores to implement all the features that the marketing team wants to put into the product.

    Regards,
    RandyP

  • What do you mean:

    "And if you are doing much floating point, then only 2 C66x cores could do what you need."

     

    Not all 8 cores can work in floating point at the same time?

    I have not read through C66x docs because I have so much to care about now. In the end product, we may be interested in fixed point calculation. But floating point is good at the beginning I think.

     

  • Robert,

    Let me restate that sentence:

                            And if you are doing much floating point, then you may be able to do what you need with as few as 2 C66x cores.

    The C66x and C674x cores have native floating point instructions, so they can do floating point operations considerably more efficiently than one of our C64x+ or earlier fixed point cores.

    My intention was to say that you can get a lot done on fewer cores with the C66x.

    Regards,
    RandyP