Should IRAM (L2 RAM) be cacheable?

Hello,

One can think the L2 IRAM will be cached only by L1 caches (see sprug82a.pdf, 1.7.4, p21).

Jakez

Hello,

Thank you Jakez for your hint. In this PDF is written:

"L2 cache is used to cache external memory addresses only; whereas, L1P and L1D are used to cache both L2SRAM and external memory addresses."

So far, so good but that is not completely that what I'm observing when I take a look into the memory browser of CCS. Here are some more details about my configuration. My C674x has got the following memory map:
-------------------------------------------------------------------------------------------------------
0x0080_0000  C674x Level2 (L2) Cache /  RAM -> local address
0x4080_0000  C674x Level2 (L2) Cache /  RAM -> global address
0x8080_0000  DDR External memory space
-------------------------------------------------------------------------------------------------------
So we have the following both use cases. First we can access the IRAM (L2 RAM) through the local addresses or second we access it through the global addresses. To use both ways at the same time is no good idea. The external memory is always access through the addresses beginning at 0x8000_0000. To get further information about this local/global thing, read here.

For the first case I can observe the following:
When I access the IRAM through the addresses beginning at 0x0080_0000 the IRAM get cached by L1D but NOT by the L2 Cache, as expected. Please take a look at the following figures.

For the second case I can observe the following:
When I access the IRAM through the addresses beginning at 0x4080_0000 the IRAM get cached by L1D AND by the L2 Cache.




Why did the IRAM in the second case get cached by the L2 cache? Is there anything that I missed?

Hello,

Maybe there's some misconfiguration; memory map from data sheet says:

- 0x00800000.. : L2 RAM; DSP access only (aka local access)

- 0x11800000.. : L2 RAM; DSP, EDMA, ... access (aka global access)

- 0x40000000..  : EMIFA SDRAM (CS0)

- 0x80000000.. : Shared SRAM (may be named L3, external to megamodule, L2-cacheable)

- 0xC0000000.. : DDR2 SDRAM

CPU access to L2 RAM via 0x01180000 seems to be preferable (avoiding pointers mess with EDMA)

Jakez

Hello,

I copied the memory map, that I posted, from my chip documentation (SPRS778A). But this file is not public available. So, I hope this memory map is ok. The link to this local/global thread should just explain the concept.

Regards
Jo

Hello,

Sorry, I supposed (by default) you use a TMS320C6747 or TMS320C6748 chip. If it is not the case, you should indicate it, helping TI people (aware of non-public docs) to help you.

Jakez.

Hello,

Sorry about not indicating it. I add a comment to the original post to clarify that.
At the beginning of this thread I thought it is maybe a generic problem.

Regards
Jo