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regarding cache programming in C6678

GS Vinoth
Prodigy 240 points

Hello , 

I was trying to execute the program provided in the               TMS320C66x         Literature Number: SPRUGY8         November 2010          DSP Cache.

page number 50 , Example 2-5 Changing L2 Cache Size Code. The CCS version is  Version: 5.1.1.00031. The hardware used is TMDXEVM6678LE Rev 1.0

I created an empty project and just complied an hello world program .( in debug mode) It complied perfectly and then i copied the above mentioned program and just replaced the already existing code with the provided example.

I copied the linker command provided in the example and replaced the existing linker command file. Since the cmd file is derived , should i make these changes in the CFG file.

I have lot of complie errors.

I need to know what are the header files to be included. 

there are certain #defines provided, like DAT_XFRID_WAITNONE, DAT_CHAANY, DAT_PRI_HIGH

what kind of header file i should use to enable these lines? DAT_open(DAT_CHAANY, DAT_PRI_HIGH,0);

#pragma DATA_SECTION(buffer_A, ”.external”). The compiler provides an error stated as below

         #7 unrecognized token main.c /cache_test line 12 C/C++ Problem, #821 badly formed pragma main.c /cache_test line 12 C/C++ Problem

Also the identifiers like "ext_data_B", "local_var_A","N_DATA_B","N_STATE_A","state_A","Uint32" are not defined. Should we define this ourselves and if so what is the type qualifier we have to use?

My installation path is in C:\ti\.... and C:\Program Files\Texas Instruments.

Kindly guide me whether any inclusion of header files will solve all the above problems or should i do anything else, like setting some path in the CCS.

Thanks in advance.

  • 0
    Intellectual 440 points

    Hi,

    Why do you want to change L2 cache size ? Do you want to do it in "runtime" and change it during execution, or is it only an initialization?

    If it is only an initialization, and if you don't want to change it later, you can set the cache size in the GEL file, or by calling CACHE_setL2Size() at the begin of your program.

    Do not forget to include

    #include <ti/csl/csl_cache.h>
    #include <ti/csl/csl_cacheAux.h>

    And, if needed, specify the include search path ( ti/pdk_C6678/packages )

  • 0
    TI__Mastermind 30825 points

    In the case of the Cache functions you'd want to include the csl_cacheAux.h header file, this is using the CSL.

    The DAT layer hasn't been created for the C66x family.  The example code was apparently re-used from another family.  The Cache portion is correct, but you'd need to use other functions such as IDMA to handle the data movement portion.

    Best Regards,

    Chad

  • 0 in reply to Chad Courtney
    Prodigy 240 points

    Hello All,

    I was trying as an to change the cache size as experiment so that i can use cache optimization. 

    With the above inputs I tried to build the code, did it , with so many hard coded paths.  The function DAT_open() has a parameter DAT_PRI_HIGH (DAT_open(DAT_CHAANY, DAT_PRI_HIGH,0))which is specified in   csl_dat as        #define DAT_PRI_HIGH    EDMA_OPT_PRI_HIGH. I understand it is a priority. But i could not find out the value for EDMA_OPT_PRI_HIGH. I searched in the "C:\ti\...." and "C:\Program File\Texas Instruments\......" folder also.                                                       Any body know how to set this value.

    Also i blocked CACHE_enableCaching(CACHE_CE00); as it was providing error. It says that it could not find out CAC2766.Cache_code+errors.docHE_CE00.

    When i went through the CSL API reference guide i found the above line to be legal.

    Also i copied the below code into the already derived linker.cmd

    MEMORY
    {
    L2_1: o = 00800000h l = 00008000h /*1st 32K segment: always SRAM */
    L2_2: o = 00808000h l = 00008000h /*2nd 32K segment:Task A-SRAM,Task B-Cache */
    CE0: o = 80000000h l = 01000000h /*external memory */
    }
    SECTIONS
    {
    .cinit > L2_1
    .text > L2_1
    .stack > L2_1
    .bss > L2_1
    .const > L2_1
    .data > L2_1
    .far > L2_1
    .switch > L2_1
    .sysmem > L2_1
    .tables > L2_1
    .cio > L2_1
    .sram_state_A > L2_2
    .sram_process_A > L2_2
    .sram_local_var_A > L2_2
    .external > CE0
    }

    I have attached my code and errors here. Kindly provide me insights on how to run this program.

    3264.Cache_code+errors.doc

    Thanks in Advance.

  • 0 in reply to GS Vinoth
    Intellectual 440 points

    Hi,

    I just have an answer for CACHE_enableCaching(CACHE_CE00);

    Do not use the CACHE_CE00, just use the MAR number.

    For exemple, if you want to enable caching for the 16MB from 0x A000 0000 to 0x A0FF FFFF, since 0xA0 = 160, just write CACHE_enableCaching(160);

    Do not forget

    #include <ti/csl/csl_cache.h>
    #include <ti/csl/csl_cacheAux.h>

    and the include search path to the CSL (ti / pdk/ packages) if the compiler can not find those headers.