Questions on Hyperlink

The following presentation may help you understand how the configuration and especially the address translation is working

Look at https://processors.wiki.ti.com/index.php/Keystone/Trainings/Reading-MAR-27-12  at introduction to HyperLink

See if it helps

Ran

Dear Ran,

              Thanks for your reply. I went through all the documents, webinars, UGs, e2e posts and others and then only coming to post my doubts on this e2e forum. please take out some time to answer All my queries [i made sure that i have read earlier e2e posts and then only posting my doubts]. I am posting only after i wasn't able to understand.

Thanks

Chandra

Chandra,

I can answer to your third question:

Hyperlink can achieve speeds less than 40 Gbps because you can configure 4 links at 12,5 Gbps each.

For your last question, I think the important point when you connect two different devices is the configuration of the hyperlink module.

You have to configure it at the same speed, the same number of lane used, ...

But I didn't try it yet, I only works on c6678.

Hi Mika,

              For Q3, i got the answer. There are 2 levels of understanding..Ports and Lanes. [I Mistook one for another]

There are 4 ports and 4 Lanes. I thought they are mapped to each other. so currently only one port is enabled, but all 4 lanes are enabled.

===========

/**  *  @ingroup hyplnklld_api_functions  

*  @brief  Hyplnk_open creates/opens a HyperLink instance  

*  *  @details This function creates a handle.  The peripheral itself  

*           is not modified.  More than one handle to the same  

*           hyperlink peripheral can exist at the same time.  

*  *  @pre     pHandle != NULL  *  @pre     *pHandle == NULL  

*  *  @retval  hyplnkRet_e status  *  *  @post    *pHandle == valid handle  */ hyplnkRet_e Hyplnk_open (   /** [in] HyperLink port number (0,1,...)   

*    * Current KeyStone devices only have one HyperLink port (port 0).    

 * The port number allows forwards compatibility if future devices   

 * have multiple ports.   

*/   int            portNum,   Hyplnk_Handle *pHandle   /**< [out] Resulting instance handle */ );

===========

Thanks

Chandra

ok,

     The main R&D i was doing was to "MAP each Core [4 Cores] to Each Lane [4 Lanes]". So that each core need not care about other core and can do asynch data transfer operation. So how to dedicate a hyperlinke lane for a core.

Since the signals are differential signals, i doubt i can do that? Can someone please confirm whether i can dedicate a lane for a core [just like a SRIO Lane can be dedicated to a core]. I am using c6670.

Thanks

Chandra

This is not my understanding about the HyperLink lanes.  In fact, I think that the number of active lanes (either one or four, but never two or three) is automatically determines by the hardware based on the traffic.  From the User Guide:

Power Management

The HyperLink transmitter actively determines the power states it enters based on the

Lane Power Management Register (see Table 3-16 on page 3-14) and informs its

correspondent receivers on the other side through the sideband signals to enter the

same power state.

During reset SerDes is held in a power down state with all lanes disabled. After exiting

reset, the HyperLink module sends a message via the sideband bus to the remote device

requesting its abilities. After the abilities are received, the HyperLink automatically

enters an operable state. SerDes is only brought out of reset if either the zero lane bit of

the PWRMGT register has been cleared or a transaction is pending. The HyperLink

module automatically changes the power mode based on the PWRMGT register

settings and the outbound load. By default, the HyperLink leaves the Tx link idle until

a transaction is received from its VBUS slave port. Then, the HyperLink enters one lane

mode to serve this transaction and the lane power up procedure for one lane is

completed. HyperLink dynamically manages its power mode based on the traffic load.

When a single lane can not keep up with the traffic load, the HyperLink module

automatically enters the four-lane mode, if it is supported. If the load drops to below

single-lane performance, the HyperLink module automatically enters the single lane

mode by powering down the upper three lanes. If the traffic load is further reduced, the

HyperLink automatically enters the zero-lane mode by disabling the single-lane mode

and shutting down SerDes until it sees the next transaction. Both transmit and receive

are independently controlled so that for certain applications only one direction may be

needed.

The transition among different modes is controlled by the lane power management

register (Section 3.2.15 ‘‘Lane Power Management Control Register (Base Address +

0x44)’’ on page 3-14).

Ok Ran,

                Thanks for your reply. Now i understand that "I CANNOT MAP (or dedicate) A CORE TO A LANE". Can you please answer my other questions.

Thanks

Chandra

I can answer question after question in generic terms. I prefer not to answer in the example context.

1. Is the example capable of destination buffer in L2SRAM, MSMCSRAM, and DDR3 [in Loop back or Board to board connection]?

Let’s understand the question.  Device A wants to read an address in device B. regardless if the address is part of the DDR, MSMCSRAM or (the global address of) L2SRAM.  Since HyperLink in device A is the memory between 0x4000 0000 to 0x4fff ffff, there need to be a translation from the address in device A to the destination address of device B.

If you read the Hyperlink document that I referred to you in the past, there are example how to configure the system to read (or write) from L2SRAM of device B, from DDR of device B and from MSMCSRAM of device B. 

 so after the correct configuration, if the code is x=*p where p points at 0x4ABC DEFG  and 0x4ABC DEFG is translated to address 0x8123 4567, then the value in x (on device A) will be the value in address 0x81234567 of the DDR that is connected to device B.

Please read it again and see if you understand how the destination translation is working.  If this is understood, tell me and we can continue.

If I miss something, please let me know

 Regards    Ran

Hi Ran,

           Thanks for reply and I understood that and following is diagram depiction

Device A [0x4ABC DEFG]            ===================> Device B [0x8123 4567]

Device A [0x4ABC DEFG+1]            ===================> Device B [0x8123 4567+1]

Device A [0x4ABC DEFG+2]            ===================> Device B [0x8123 4567+2]

.

.

.

on device A, i have to input the address 0x8123 4567 [This address should be known apriori to Device A to transfer data to Device B at location 0x8123 4567] [Device B or Remote Device address], so that it maps to 0x4ABC DEFG [which is Hyperlink translated address].

I checked the example for loopback, it works for L2SRAM, MSMCSRAM and DDR3. [i experimented on c6670 board].

Thanks

Chandra

Hi Ran,

                If my understanding is correct. can you please move to my next question.

Thanks

Chandra

2. why is this SMS or SES MPAX registers must be configured ? what purpose do they achieve [please tell in this particular hyperlink example project context]

"If this is placed in MSMC or DDR RAM, then the SMS or SES MPAX must be configured to allow the access "

You must know that when a core reads an address there is a translation between the logical address and the physical address. This translation is done by teh MPEX registers, and it is translation from 32bit of the address bus to the 36bit to access the DDR (for example).  Did you ask yourself how the system can address 8GB where there is only 32bit address bus - the MPAX registers do the translation.

Each core has a set of MPAX registers. 

But what happen if the memory request comes from another master, not a core? then there is a set of registers that handle this case. These are the SES (System EMIF Slave) and the SMS (System MSMCSRAM Slave) registers. And these registers need to be set if another master tries to access DDR or MSMCSRAM through the teranet (as a slave)

Look at the MSMC User Guide. I use 6678 so in this document look at

2.1.2 System Slave Interfaces

If you want to understand more about the translation that is done you can look at the attached document.  This is NOT an officail TI presentation but it can give more insight.

7674.XMC External Memory Controller.pptx

Hi Ran,

            Few points on what u told

A. Lets say, if i am only addressing till 2GB of external DDR [DDR Start address at 0x8000 0000 to 0x8FFF FFFF], then "I SHOULD NOT WORRY ABOUT MPAX SES OR SMS OR ANY ADDRESS TRANSLATION". Assuming my Src and Dst buffers are in DDR and my access is within 2 GB?

B. If only if my hyperlink translation requires more than 2GB, then only i need to worry about SMS MPAX or MPEX?

C I went through the .pptx already and understand the address translations [i got the .pptx from your previous posts]. Thanks for the same.

D. Say, if i am accessing device B from device A [device A --> device B], since device A is master [since device A is external device and is master] [and is not one of the cores on device B], i need to enable SES MPAX or SMS MPAX. Say my access from device A to device B is limited to within 2GB, still do i need to write those registers [SES and SMS] ? [I assume i dont require any MPAX stuff here as i am not doing any mapping or address translation from logical address [32 bit within board address] to physical address] [36 bit OUT of board address].

Thanks

Chandra

One important thing is that the default settings of the MPAX registers is indeed no translation, that is, logical = physical.

My guess is that the SES and SMS default is the same.  (Guess = Not sure), so if you do not manipulate any MPAX registers and you access only the lower 2GB of DDR you do not have to worry about the registers.

So try it, drop the setting in the example. And don't forget to tell me the result

Best wishes   Ran

Hi Ran,

             Already i have tried and i was able to transfer data [loopback] from DDR to DDR without any SES and SMS MPAX stuff. that's where i saw that comment and got confused as "why i need to do SES and SMS MPAX". Once i do the experiment between two boards using cables. i wil surely update this post.

Thanks

Chandra

Hi Ran,

             Questions 3 is answered/explore already and also i did edma code [so question 4 is solved].

Kindly answer question 5 and 6.

Thanks

Chandra

Hi Ran,

            I am awaiting your response.

Regards

Chandra

I am OOO, please wait for me to return back

Chandra

Question number 6 and 7.   I see no reason why the same scheme that you mention will not work for buffer that is larger than 128MB (but not larger than 256MB).  Of course the number of bits for the remote offset should be set accordingly (The RX segment size)

About question 7 – The HyperLink translates addresses.  In fact, if you look carefully in the User Guide it is clear that it can support devices with 36bit address bus.  I see no problem with communicating between different devices, as long as both support HyperLink.

Please get back to me and tell me if you are OK or need more support

Best Regards

Ran