Hi,
I'm currently working in a design using the TMS320TCI6614 and am seeking to know if my understanding of the use of the PHYSYNC and RADSYNC signals for the AIF2 module is correct. I've read the documentation and some forum posts about these signals but still want to make sure we are using them correctly in our system. I'm attaching a block diagram of our current connectivity to illustrate our architecture.
Looking at the diagram you can see that our FPGA selects timing information from one of a variety of sources. This serves as the master timing signal for the node. RADSYNC and PHYSYNC are then generated from the FPGA and fed to the DSP. As the diagram illustrates, we have 4 links allotted to systems off board. Assuming that the off board links are implemented as CPRI, it is my understanding that all timing and framing information is contained within the protocol's packets, and that the PHYSYNC and RADSYNC signals need only be fed to the DSP from the node's master timing source. (In this case the FPGA with it's timing inputs.) Furthermore, I'd like to know if the two SYNC signal need to be synchronous with any external events. From my reading this seems not be the case.
Please comment on my understanding, questions, and the implementation in general as needed. We want to make sure we get this straight.
Thanks
Kevin
