gel files for DDR software leveling

Andrew Dyer

I notice in the .gel files from TI and spectrum digital for doing software leveling on the DDR that it looks like the the ratio values (3,2,1,0) are assigned to the wrong registers (0,1,2,3).

ex.

WR_MEM_32(DDRPHY_CONFIG_BASE + 0x0F0, (DDR3_WR_DQS_RATIO3 << 10) | DDR3_WR_DQS_RATIO3);

According the TRM offset 0x0f0 is DATA0_REG_PHY_WRLVL_INIT_RATIO_0, but it's getting data from the RATIO3 define.  Since RATIO0-RATIO3 are defined with identical values, nothing happens, but it is confusing.

over 13 years ago

0 Pavel Botev over 13 years ago

TI__Guru**** 170625 points

Hi Andrew,

I think the evm816x gel file is correct, at least it is aligned wit the evm816x u-boot source code, in which we have the following description (ddr_defs_ti816x.h):

/*
* This represents the initial value for the leveling process. The
* value is a ratio - so 0x100 represents one cycle. The real delay
* is determined through the leveling process.
*
* During the leveling process, 0x20 is subtracted from the value, so
* we have added that to the value we want to set. We also set the
* values such that byte3 completes leveling after byte2 and byte1
* after byte0.
*/
#define WR_DQS_RATIO_0       0x20
#define WR_DQS_RATIO_1       0x20
#define WR_DQS_RATIO_2       0x20
#define WR_DQS_RATIO_3       0x20

Thus we have:

DDR3_WR_DQS_RATIO3 -> data0 writelvl init ratio -> DATA0_REG_PHYWRLVL_INIT_RATIO_0

DDR3_WR_DQS_RATIO2 -> data1 writelvl init ratio -> DATA1_REG_PHYWRLVL_INIT_RATIO_0

DDR3_WR_DQS_RATIO1 -> data2 writelvl init ratio -> DATA2_REG_PHYWRLVL_INIT_RATIO_0

DDR3_WR_DQS_RATIO0 -> data3 writelvl init ratio -> DATA3_REG_PHYWRLVL_INIT_RATIO_0

Best Regards,

Pavel

0 Andrew Dyer over 13 years ago in reply to Pavel Botev

Intellectual 650 points

I originally started with this gel file:

http://processors.wiki.ti.com/index.php/File:TI816x_ddr3.zip

lines 1995-2012

    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x0F0,DDR3_WR_DQS_RATIO3); /* data0 writelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x0F4,0x00000);   /*   */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x194,DDR3_WR_DQS_RATIO2); /* data1 writelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x198,0x00000);   /*   */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x238,DDR3_WR_DQS_RATIO1); /* data2 writelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x23c,0x00000);   /*   */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x2dc,DDR3_WR_DQS_RATIO0); /* data3 writelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x2e0,0x00000);   /*   */

    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x0FC,DDR3_RD_GATE_RATIO3); /* data0 gatelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x100,0x0);
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x1A0,DDR3_RD_GATE_RATIO2); /* data1 gatelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x1A4,0x0);
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x244,DDR3_RD_GATE_RATIO1); /* data2 gatelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x248,0x0);
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x2E8,DDR3_RD_GATE_RATIO0); /* data3 gatelvl init ratio */
    WR_MEM_32(DDRPHY_CONFIG_BASE + 0x2EC,0x0);

I thought I had seen the same code in the Spectrum Digital gel file, but it appears I was mistaken about that one.

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gel files for DDR software leveling