I wrote some code (under SYS/BIOS fwiw) to use SPI1-CS0 to transfer data. The SPI clock frequency was set to 12MHz. I tested it both using an ISR to transfer data to and from the FIFO, and using the EDMA controller.
When I put a scope on the clocks, I saw a gap between the 8 clock byte groups. With the EDMA, there was a 500ns delay between bytes. Using the ISR to move data to the FIFO, the gap went down to 200ns. It did not matter whether it was tx only or tx/rx mode.
I could not find an explanation or quantification of this phenomena in either the TRM or the timing information in the DS. How can I get rid of that dead time?