SRIO DirectIO from/to DDR?

Hello Alberto,

I'm looking up the SRIO User Guide right now and hope to have an anwser for you real shortly.

Thanks

Elush Shirazpour

Alberto,

The SRIO Direct IO does not need the multicore navigator to send/recieve data. The CPPI, or multicore navigator, is independent of the SRIO Direct IO. For Direct IO transmit operations, the user needs to work with the LSU shadow registers.

You can access the SRIO User Guide at http://www.ti.com/lit/ug/sprugw1a/sprugw1a.pdf to look up examples.

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Thank you

Elush Shirazpour

Hi,

Thanks, you confirm my interpretation of the srio user guide, but my real problem is if it can write/read to L2 only or also to DDR. Looking on sprigw1 overview ant block diagram it seems it is connected to L2 only (that include L2SRAM and MCSM)

Alberto,

The DDR communicates with the TeraNet Switch Fabric through the MSMC. So the SRIO will have to communicate with the TeraNet to the MSMC to the DDR.

Thank you

Elush Shirazpour 

Alberto,

To go into further detail, the SRIO can not communicate directly with the DDR.

Thanks
Elush Shirazpour

So, to summarize:

1. with SRIO DirectIO from an external device (e.g. FPGA) I can write/read only to L2SRAM and also to  MCSM (4 Megabytes) For instance, a destination address 0x0C000000 will result in a transfer from FPGA to MCSM.

If I use a doorbell to signal the end of transfer, when the doorbell arrives all previous SRIO tranfer are already completed and It is possible to immediatly launch an EDMA to transfer from MCSM to DDR.

2. To operate on the DDR, I have to send SRIO messages (up to 16 SRIO packets per transactoin) on a Multicore Navigator queue and then I can move automatically to DDR by proper programming the multicore navigator.

Is that correct?

Well, I'm still a bit confused. Just to say it in pratical terms, my question is: can an external FPGA write directly to the DSP DDR3 by sending an SRIO DirectIO packet (NWRITE) with desitnation address 0x80000000, without DSP CPU intervention ?

I interpret your last message as a "yes": the SRIO "write" to the MCSM that route the writes to the DDR, and  this "routing" doens't  require any special setup by the CPU.

Alberto,

Your intrepretation is correct. I didn't mean to confuse you before.

Thank you

Elush Shirazpour

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Alberto,

i think you should try having your fPGA write to a DDR address. My fpga writes to 0x80000000 all the time and then sends a doorbell.  Search for my name and srio to find a lot of posts that go over this.

on the other if you want the dsp to send out a dio message, you do have to have in l2 or msmcsram for the Lsu to work.

brandy

BrandyJ said:

i think you should try having your fPGA write to a DDR address. My fpga writes to 0x80000000 all the time and then sends a doorbell.  Search for my name and srio to find a lot of posts that go over this.

Thanks, I'll look for.

on the other if you want the dsp to send out a dio message, you do have to have in l2 or msmcsram for the Lsu to work.

I did a very simple test program that, internal loopback core 0 only, send (NWRITE) from L2SRAM to DDR and then from DDR to L2SRAM. At first glance both works, while, If I understand, You say it should not work from DDR.

I haven't yet tested with READ, but I suppose that if write works, read works also.

Alberto,

For more detailed information, try looking at this E2E: http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/215645.aspx

Thanks

Elush