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SRIO to DDR3 using MAU

Blake Carpenter
Expert 6975 points

Hi,

Currently we have a TI C66x demo card exercising SRIO to move data back and forth to our custom card that has a big FPGA on it.  The interface is SMC on the demo card side and XMC on the FPGA side.  The high speed data comes from the FPGA and we want to transfer it to DDR3 on the C66x card.

We want the FPGA to initiate Ftype 6 packets and fill these with data and send them back over the SRIO to the C66x and then have it automatically move that data into DDR3.  We are not sure how this automatic movement should work for best operation...  We think MAU to DDR3?

The basic packet forming and bi-direction data transfer over SRIO is working, but the step where the Ftype 6 packets moving data to the DDR3 is not working.  Currently we have the data going directly into L2 SRAM rather into DDR3.  We do not have the DDR3 core initialized and aren't sure how to do this.  We just found out about the Platform Library.  Is this what we should be using to configure the DDR3?

We think that by using direct I/O and the MAU, we should be able to take the incoming data and make it automatically transfer into DDR3 rather than L2 Cache which we think is happening now.  The crux of our problem is how to get incoming data into DDR3.

We have looked at the following e2e thread and are confused:

 http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/215645.aspx

 The Demo code TI has (that we have found) uses Ftype 9 packets and is of limited use.

 Does TI have any source code that exercises the MAU or shows MAU configuration.  Also, does TI have code that sets up the DDR3 core. The eval doesn’t appear to do this? Typically eval bds supply the initialization code and for the DDR3 on the eval?  Is this in the Platform Library.  Is this what we should be using to configure the DDR3?

We are going to try and see if data can be moved automatically by the MAU to DDR3 based on writing to the DDR3 address range alone, but aren’t certain if this is the correct approach (or if more automatic configuration is needed).

  • 0
    TI__Guru* 84110 points

    Which C66x EVM are you using? We have several.

    Which boot mode is the EVM configured for? This would be the setting of the DIP switches. Most likely, it is set for one of the demos that run out-of-the-box, but if you have changed any of these to the emulation boot mode, then there might not be DDR3 initialization being done. Other boot modes might not setup the DDR3 either, so we need to know which one.

    Further, the SRIO will have to be enabled by the C66x code before that module will work, but if you have data going to L2 SRAM, then you must have that working.

    Since you have data going to L2, what target destination address are you specifying?

    Your data should not be going into L2 Cache or it will crash the system; it should be going to L2 SRAM and eventually you will get it working to put the data into DDR3.

    With DirectIO, you specify the target destination address and if that is at 0x80000000, then you should be writing directly into DDR3. Assuming it is initialized, of course.

    The MCSDK 2.x is the software suite with all of the libraries that you will need for the C66x EVM board, whichever one it is.

    If the MCSDK includes a DirectIO example, it may be setup in loopback mode. The write would be initiated by writing to one of the LSUs with the same information that you are using to construct the transaction in your FPGA. This would not directly help you get your application working, but could be worth looking at and trying it out. Sorry, but I am not sure which project to send you to or whether there is a DirectIO example in there, but there "should" be one. We will find someone with more insights there after you have addressed some of these clarifying questions.

    Regards,
    RandyP

  • 0
    TI__Intellectual 2790 points

    Hello Blake,

     

    Are you asking how to write to the DDR3 from SRIO or what is the best route to write from SRIO to DDR3 or both?

     

    I am not sure if TI has any MAU configuration or DDR3 core code, but I will look into that.

     

    When I wrote code that I needed the information to go into the DDR3, I used a #pragma in CCS. Are you familiar with #pragma? I would be able to save a SRIO register or functions in the DDR3 using the #pragma decleration.

     

    Thank you

    Elush Shirazpour 

  • 0
    Prodigy 30 points

    Which C66x EVM are you using? We have several.

    We are using TI TMX320C6657 Lite Evaluation Module

    Which boot mode is the EVM configured for? This would be the setting of the DIP switches. Most likely, it is set for one of the demos that run out-of-the-box, but if you have changed any of these to the emulation boot mode, then there might not be DDR3 initialization being done. Other boot modes might not setup the DDR3 either, so we need to know which one.

    The device is configured for out-of-box demo boot mode. After initial boot-up, we use the emulator for program loading/testing.

    Further, the SRIO will have to be enabled by the C66x code before that module will work, but if you have data going to L2 SRAM, then you must have that working.

    Yes.

    Since you have data going to L2, what target destination address are you specifying?

    We are currently using addresses within CorePac0 L2 SRAM (returned by Osal_srioDataBufferMalloc(),starting at 0x10800000)

    Your data should not be going into L2 Cache or it will crash the system; it should be going to L2 SRAM and eventually you will get it working to put the data into DDR3.

    This is correct. The data was being transferred to L2SRAM.

    With DirectIO, you specify the target destination address and if that is at 0x80000000, then you should be writing directly into DDR3. Assuming it is initialized, of course.

    I’ve just stumbled across an initialization routine in the platform library, platform_init(), which initializes the DDR3 memory. I have modified the DIO example to write directly into the DDR3 memory and it works.

    Thank you so much for your quick response. The next thing I want to do is to have BIOS use DDR3 for heap memory (i.e. I want to let malloc/free manage the memory in DDR3). How do I go about doing that? 

  • 0 in reply to Robert Stevens
    TI__Guru* 84110 points

    Robert,

    We are very glad you have the SRIO operation working the way you need it to. I have marked your reply above as Answered, since this thread was addressing the DirectIO question and you described how you solved it.

    Your new question needs to be posted into either the BIOS Forum under Embedded Software or the Compiler Forum under Development Tools, depending on whether you mean to use SYS/BIOS' Mem_alloc/Mem_free or the C compiler malloc/free. SYS/BIOS is probably the best choice because of its greater flexibility and the additional allocation options that you have, like uniform blocks of memory.

    "How do I...?" usually means you need to go to the TI Wiki Pages and search for "SYS/BIOS training" (no quotes). We have a lot of resources available to help you learn how to get the most from our tools. You can take a class in person or online or read the material that is posted online.

    Depending on how your platform is configured in your CCS project and SYS/BIOS, it may already be in DDR3. Or maybe you just need to set the heap size, or add the heap module in SYS/BIOS. The training material will help you get to where you need to be.

    Regards,
    RandyP

  • 0 in reply to RandyP
    TI__Intellectual 2790 points

    Randy,

     

    I used a #pragma to save a struct that I created. I did  “#pragma DATA_SECTION(Hibr_Srio, ".sriosection");” The Hibr_Srio was my struct and “.sriosection” was the name I placed it as to be directed to DDR3.

    I placed the .sriosection in my unitTest.cmd file in CCS as “.sriosection:      load >> DDR3” so that CCS knew to save that variable (Hibr_Srio) in the DDR3.  I worked with the SRIO loopback example so I did not create my own unitTest.cmd file.

    I hope that was clear.

     

    You can also do the same with "#pragma CODE_SECTION(function_name, ".savedsection");". The function_name is the name of the function I want saved. I do the same thing I do before into the unitTest.cmd file as well.

     

    Thanks

    Elush