Precision of C6678 DDR3 Track Impedance

g.f.

Hi,

I have a question about C6678 DDR3 Track Impedances.
I saw the following post:
http://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/120284.aspx

I understand that 50ohm for single ended signal and 100ohm for differential signal.
But we want to know the precision of the each impedance.

I read the DDR3 design guide(SPRABI1A).
UDIMM can be connected to C6678 DDR3 I/F,
so I read the JEDEC Standard No.21c to check the precision of impedance.
In JEDEC Standard No.21c, the precision of impedance was ±10% or ±15% .
So, what is the value of the precision for C6678 DDR3 track impedance?

best regards,
g.f.

over 12 years ago

0 Tom Johnson 16214 over 12 years ago

TI__Mastermind 46460 points

g.f.,

We recommend a PCB fabricator that can hold the track impedance tolerance to +/-10%. However, the circuit / board designer is responsible for DDR3 layout validation. This validation requires simulation to validate the timing and signal integrity. You should model the board PCB layout impedance extremes to make sure the timing and SI requirements are met.

Tom

0 g.f. over 12 years ago in reply to Tom Johnson 16214

Guru 15520 points

Hi Tom,

Thank you so much.
So, recommend track impedance is 50ohm+/-10% (45ohm-55ohm) for single ended
and 100ohm+/-10% (90ohm-110ohm) for differential.

best regards,
g.f.

0 Tom Johnson 16214 over 12 years ago in reply to g.f.

TI__Mastermind 46460 points

g.f.,

As stated previously, there is no single, perfect answer. Simulation is required for design validation. The document attached below addresses these issues. It has a discussion on PCB routed imdenace at the end.

7343.DDR3 routing impedances.pdf

Tom

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Precision of C6678 DDR3 Track Impedance