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AM335X UART5 setting issue

Marco Wang1
Prodigy 110 points

We try to use UART5 as BT interface,and modify mux33xx.c file but it didn't work.Is there any patch regarding to UART5?

kernel version:3.2.0

the uart5 pins config are 

{"mii1_crs.uart5_ctsn", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
{"mii1_rxerr.uart5_rtsn", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
{"mdio_data.uart5_rxd", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
{"mdio_clk.uart5_txd", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
{NULL, 0},

the mux33xx.c patch:

diff --git a/arch/arm/mach-omap2/mux33xx.c b/arch/arm/mach-omap2/mux33xx.c
index 150e478..5a06946 100644
--- a/arch/arm/mach-omap2/mux33xx.c
+++ b/arch/arm/mach-omap2/mux33xx.c
@@ -232,10 +232,10 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                "mcasp1_axr2", "mmc2_dat3", "mcasp0_axr2", "gpio3_0"),
        _AM33XX_MUXENTRY(MII1_CRS, 0,
                "mii1_crs", "rmii1_crs_dv", "spi1_d0", "i2c1_sda",
-               "mcasp1_aclkx", NULL, NULL, "gpio3_1"),
+               "mcasp1_aclkx", "uart5_ctsn", NULL, "gpio3_1"),
        _AM33XX_MUXENTRY(MII1_RXERR, 0,
                "mii1_rxerr", "rmii1_rxerr", "spi1_d1", "i2c1_scl",
-               "mcasp1_fsx", NULL, NULL, "gpio3_2"),
+               "mcasp1_fsx", "uart5_rtsn", NULL, "gpio3_2"),
        _AM33XX_MUXENTRY(MII1_TXEN, 0,
                "mii1_txen", "rmii1_txen", "rgmii1_tctl", NULL,
                "mcasp1_axr0", NULL, "mmc2_cmd", "gpio3_3"),
@@ -276,10 +276,10 @@ static struct omap_mux __initdata am33xx_muxmodes[] = {
                "rmii1_refclk", NULL, "spi1_cs0", NULL,
                "mcasp1_axr3", "mmc0_pow", "mcasp1_ahclkx", "gpio0_29"),
        _AM33XX_MUXENTRY(MDIO_DATA, 0,
-               "mdio_data", NULL, NULL, NULL,
+               "mdio_data", NULL, "uart5_rxd", NULL,
                "mmc0_sdcd", "mmc1_cmd", "mmc2_cmd", "gpio0_0"),
        _AM33XX_MUXENTRY(MDIO_CLK, 0,
-               "mdio_clk", NULL, NULL, NULL,
+               "mdio_clk", NULL, "uart5_txd", NULL,
                "mmc0_sdwp", "mmc1_clk", "mmc2_clk", "gpio0_1"),
        _AM33XX_MUXENTRY(SPI0_SCLK, 0,
                "spi0_sclk", "uart2_rxd", "i2c2_sda", NULL, 

  • 0
    TI__Mastermind 39490 points

    One suggestion would to verify there is not a conflict in the pin mux. Can you verify that the setting for the pins are what you expect? In the TRM spruh73f please confirm in the control module section 9.3.50 for the appropriate pin (0x44e10800 + pin offset) has the value you expect.

    Does your board have ethernet on it? The concern would be if you started with the board file (arch/arm/mach-omap2/board-am335x.c shipped with the SDK you might have a conflict if the ethernet portion of the initalization is not removed.

    Your patch to the mux file looks correct. The only to verify though is to look at the control register module referencing your pin to make sure it is want you want.

  • 0
    Expert 2370 points

    Hello Marco,

    could you solve your problem? I'm using following pins:

    /* Module pin mux for uart5 */
    static struct pinmux_config uart5_pin_mux[] = {
            {"rmii1_refclk.uart5_txd", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
            {"mii1_col.uart5_rxd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT},
            {"mii1_rxerr.uart5_rtsn", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
            {"mii1_crs.uart5_ctsn", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
            {NULL, 0},
    };

    rx and tx are both functioning, but I cannot set RTS high/low. Osci shows only one level - low (logically high). I made debug output in omap_mux_init_signal() routine and can confirm, that both mii1_rxerr and mii1_crs appear only once. So no conflicts.

    Yegor

  • 0 in reply to Yegor Yefremov
    Prodigy 110 points

    Hello rfc2217,

    it worked on our board with BT function which means the RTS should be ok.

    Marco

  • 0 in reply to Marco Wang1
    Expert 2370 points

    Hello Marco,

    what kind of BT have you used? From TI (wl127x) or something else?