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uPP start signal

dp
Intellectual 990 points

I'm using uPP to receive image data from FPGA, but have some puzzle about start signal:

1. Could the FPGA output the start signal on the first data_enable signal ?  that means, a start signal with many enable signals.

2. Is there any idea about the frame synchronization?

Thanks in advance.

dp

 

 

 

 

  • 0
    TI__Guru* 84110 points

    DP,

    Which device and board are you using?

    The START signal should conform to the timing diagrams shown in the uPP User Guide for the device you are using. The use of the START signal is described there, so please tell us any specific questions you have about those descriptions.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 990 points

    RandyP,

    I'm using EVM6657L board.

    According the timing graph in the uPP user's guide, one start_signal could have several relevant enable_signals. 

                            __ 
    start:     ____|   |_______________________________________________________________
                            _______________           __________________          __________________
    enable: ____|                                   |____|                                         |____|                                         |____

    Could that be right ?

    dp

     

     

  • 0 in reply to dp
    Mastermind 7980 points

    Hi,

     

    I have a same ploblem. I'm also using uPP(C6655) to receive data from FPGA with start signal.

    but, I can not receive the data correctly. After the enable signal is inactive, uPP does not receive the data when enable signal become active again.

    In order to receive the data successfully, It seems that it is necessary to reactivate start signal and enable signal.

    So please tell me the role of start signal and correct timing graph.

     

    Best regards,

    Chi

  • 0 in reply to UNA
    Intellectual 820 points

    Is there an answer to this question yet? I want to use the uPP in receive mode but I'm not sure what is the function of the START signal. My question is similar, but perhaps I can explain with an example:

    The uPP User guide says START indicates the first word of a line, but the DMA ByteCount also determines the length of a line, so which takes precedence? Let's suppose the byte count is set to 10 because we expect five 16-bit words per line. The hardware is organised to assert START=1 on the first word and START=0 on the other four. Everything presumably is fine until there's a framing sync error.

    If the START arrives early, (there's a missing data word) does the DMA skip ahead to the next line to continue storing in the right place in memory, or continue with BCNT and have all the following lines mis-aligned? If the latter, does it get back in sync at the start of the next window, or does it 'steal' the first word of the next window in order to fulfil the BCNT x LNCNT of the current window, and never get in sync again?

    If the START arrives late, (there's an extra data word or noise on the CLOCK) does the DMA store the extra word or ignore it? If it's stored, where does it go?

  • 0 in reply to Roy Jackson
    Intellectual 820 points

    On another thread, http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/t/118511.aspx Joe Combes has partly answered the question about START arriving early:

    If START is asserted before the previous line is "complete," this should result in an error.  The internal DMA expects all lines (within a single transfer) to be the same length.

    Joe, or anyone, would that error result in a UOR event, or would it simply fail to operate correctly? How would we know if that error happened, and how would we recover from it - do a channel reset? I had assumed UOR occurs when the DMA doesn't keep up with the CLOCK signal, i.e. it's a FIFO under/overrun.