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AM3352 DDR2 Trace Length and Tuning

Randy Maruschock
Intellectual 320 points
Other Parts Discussed in Thread: AM3352

I have a design using the AM3352 an a single DDR2 RAM chip.  How critical is the tuning of the DDR2 lines for matched length?  When reviewing the Beagle Bone and the AM335x Eval Board the DDR traces look to have a fair bit of delay tuning.  I'm struggling to get my tools to cooperate (or I don't have the license, trying to figure that out).  I have no doubt tuning the lines is optimal, but is it critical?  Will I be able to get by if I just keep the DDR2 traces as short as possible and specify controlled impedance to my board manufacturer?

  • 0
    TI__Guru 63145 points

    The DDR2 Routing Guidelines section of the AM335x Data Sheet defines the PCB layout requirements.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 320 points

    Thank you for the response.  I did see section 5.4.2.2 addresses the DDR2 routing guidelines.  This is my first high speed design so I'm going through a learning curve here.

    While section 5.4.2.2 outlines the constraints, and this post helped explain those constraints, the datasheet doesn't tell me what badness will happen if violate the skew and nominal trace requirements.  Are things moving fast enough that if the skews are too large than the address/data lines can be changing out of synch with the clocks?

    Do the tolerances work out that if i have a nominal tolerance on my address lines of +/- 50, and a max skew of 100, than the min and max allowable trace lengths on the address lines is +/- 150 mils?  Or do the nominal trace length and skew specs for the address lines basically state the same thing... the longest and shortest address lines need to be within 100 mils of each other?