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Boot pin problem in TMS320C6745

Rajarama M Bhat
Intellectual 550 points
Other Parts Discussed in Thread: TMS320C6745

Hi,

We are working on TMS320C6745 custom board. Out of 7 boards 1 is not able to boot from SPI1 flash.
We tried following steps:
1)Initially we tried connecting through the debugger. It successfully got connected ,when we ran a
debug gel file,we could see the bootmode as SPI0 EEPROM,even though we had configured it to be SPI1 flash.
We were able to read from the flash,write to the flash and our applications were successfully running after loading
from JTAG,except that SPI0 communication was not working.
2)We confirmed that power on sequence and voltage levels for core and I/Os are fine
3)We are providing a stable system clock from a 24Mhz crystal oscillator.
4)Reset delay to TMS320C6745 is fine according to datasheet.Our understanding is
that it requires a minimum of 100ns of reset delay.
5)Since boot[1] register was always low(no matter what) ,we isolated boot[1] pin on TMS320C6745 and connected
it to external strong pull up. When we measured the voltage on the pin it was always 3.3V ,but the boot[1] register
was reading zero.

Can somebody please suggest if there is anything else needs be checked or missing ?
We are facing this issue from a long time, we really appreciate a fast response.
If we are successful in solving this problem, we intend to go for production.

Thanks and Regards,
Rajaram

  • 0
    TI__Expert 7470 points

    Rajaram,

    Have you considered soldering problems on this particular board? This seems to be the case since the strong pullup on boot pin is not being latched by the device. The difference in boot pin config for SPI0 EEPROM vs SPI1 Flash is boot[2] pin = 0 vs 1. Do you set up pin muxing for SPI0 in your application? Can you try resoldering the device on the board?

    Please also remember that the boot config pins are not latched on a warm reset. They are only latched on a POR. See info on wiki link here: http://processors.wiki.ti.com/index.php/OMAP-L137_Bootloader.

    Regards,

    Sunil Kamath

  • 0 in reply to Sunil Kamath
    Prodigy 150 points

    Dear Sunil,

    This is Nrupathunga. Thanks for your inputs.  

    In our design, RESET for the C6745 is given by Master Device and TRST is pulled up.

    • I  have isolated all boot pins required for SPI1 Flash configuration from Master device and connected pullup and Pulldown resistors accordingly.
    • I  tried by pulling down TRST to GND through 10K resistor. Emulator connection itself is failed for this modification.
    • I  tried by isolating RESET from master device  and connected RC delay circuit for this. Still It is showing as SPI0 EEPROM Mode only.
    • I  tried by  adding RC delay circuit for TRST as shown in attached Schematic.  Started  to showing different mode configurations for every power cycle. Like HPI, I2C0 Master, NAND8 , NOR, INVALID.... but never showed expected configuration i.e SPI1 FLASH.

    I have probed all boot pins required for SPI1Flash Configuration and observed that status are not changing and all are as per resistor configurations: i.e  boot7=0 ; boot2=1; boot1=1, boot0=0; boot3=0.

    Please review attached schematic and suggest what  could be reason for this issue.

    Regards

    Nrupathunga2867.TMS320C6745_Boot_Configurartion_Issue.docx

  • 0 in reply to Nrupathunga Somachari
    TI__Expert 7470 points

    Hi Nrupathunga,

    As given in section 6.5 in the C6745 datasheet (sprs377d), the TRST pin should be held low during a POR. This is required for the emulation, PLL and boot logic to initialize correctly. Your POR should happen correctly if you follow the LCDK example. Please confirm that the POR in your experiments follow the requirements in Table 6-2 and Figure 6-4 (check signals on scope). If you are using a third-party JTAG controller see http://processors.wiki.ti.com/index.php/Emulation_FAQ#How_should_the_connection_to_the_TRST_signal_be_terminated.3F

    Nrupathunga Somachari said:
    I have probed all boot pins required for SPI1Flash Configuration and observed that status are not changing and all are as per resistor configurations: i.e  boot7=0 ; boot2=1; boot1=1, boot0=0; boot3=0.

    Did you check state of all boot pins at the time of reset?

    Schematics does not indicate if the TRST pin isolated in your RC experiment. Why do you have a mix of 3.3V and 2.5V?

    To check if the boot pins are correctly soldered on to the board - you can run a GPIO test to drive the Boot pins and check on scope.

    Regards,

    Sunil Kamath