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DDR2 Clock Jitter

Jeroen van Andel
Prodigy 60 points

We are using the TMS320C6748BZWT3 DSP with a 1Gb DDR2 SDRAM (Elpida EDE1116AEBG-8E-F)

When measuring the DDR Clock at the DDR device we noticed that the clock jitter is higher than the requirements for the DDR (see Clock Jitter table on page 19 of the DDR datasheet).

 The jitter is measured with the following setup:

  • Oscilloscope : Tektronix  DSA72504D (25GHz)
  • Probe : Tektronix P7313 (12.5GHz)
  • Running DDR Analysis Tool

 Results from jitter measurement  (fails marked red):

 

Description

Requirement DDR 800

Mean

Std Dev

Max

Min

p-p

Max-cc

Min-cc

 

Min

Max

 

 

 

 

 

 

 

tJIT(per), CK

-100ps

+100ps

NA

NA

93.711ps

-87.383ps

NA

NA

NA

tJIT(duty), CK

-100ps

+100ps

NA

NA

61.827ps

-58.027ps

NA

NA

NA

tJIT(cc), CK

-

200ps

2.0161fs

29.286ps

138.88ps

-124.12ps

263.00ps

222.40ps

-231.36ps

tERR(2per), CK

-150ps

+150ps

NA

NA

120.22ps

-145.35ps

NA

NA

NA

tERR(3per), CK

-175ps

+175ps

NA

NA

163.73ps

-175.78ps

NA

NA

NA

tERR(4per), CK

-175ps

+175ps

NA

NA

210.30ps

-192.25ps

NA

NA

NA

tERR(5per), CK

-175ps

+175ps

NA

NA

246.67ps

-242.30ps

NA

NA

NA

tERR(6-10per), CK

-300ps

+300ps

NA

NA

448.78ps

-427.11ps

NA

NA

NA

tCH(avg), CK

0.48..0.52 tCK (avg)

501.11mtCK(avg)

106.05utCK(avg)

501.41mtCK(avg)

500.73mtCK(avg)

682.69utCK(avg)

37.818utCK(avg)

-31.491utCK(avg)

tCL(avg), CK

0.48..0.52 tCK (avg)

498.89mtCK(avg)

106.05utCK(avg)

499.27mtCK(avg)

498.59mtCK(avg)

682.69utCK(avg)

31.491utCK(avg)

-37.818utCK(avg)

 

  • DRAM Clock is 150MHz
  • The input clock of the DSP (40MHz) has a period jitter of approx. 29ps.
  • The noise on the DSP and DRAM supplies are all < 60mV (including the PLL0 and PLL1 supply)

 Do you have any idea what can cause the jitter?

  • 0
    Prodigy 60 points

    Hello,

    Any update on this issue? 

    Do you have some reference measurements of the DDR2 clock output jitter on other designs?

    BR,

    Jeroen

  • 0 in reply to Jeroen van Andel
    TI__Expert 4760 points

    Jeroen,

    We start with the PCB Board Layout perspective.

    How about the DDR clock trace routed over the board and their Terminations.

    Did you check the adequate ground plane and power plane reference and enough decap placed near the device.

    Did you face any random Read/Write Fail

    Regards

    Antony  

  • 0 in reply to Antony Samsunil
    Prodigy 60 points

    8255.TI.ZIP

    Hello Antony,

    Thanks for the feedback.

    We have an 10 layer PCB with the following stackup

    TOP

    Top placement and routing

    INT1

    GND

    INT3

    Routing

    INT5

    Routing

    INT7

    Power

    INT8

    Power

    INT6

    Routing

    INT4

    Routing

    INT2

    GND

    BOT

    Bottom placement and routing

    All DDR signals are routed on : TOP, INT2, INT4 and BOT.

    The clock is routed on INT3. I attached screenshots of the clock roting (DDR2_CK_TOP.PNG, DDR2_CK_INT1.PNG,  DDR2_CK_INT3.PNG and  DDR2_CK_INT5.PNG) We do not have series termination in the DDR signals.

    I also attached the schematic of the DDR and the decoupling of the DSP (DDR2.pdf)

    We did not see any Read/Write Fails but the clock jitter is not within the JEDEC requirments.

    Do you also have some results of the clock jitter on other (reference) boards?

    Best regards,

    Jeroen

  • 0 in reply to Antony Samsunil
    Prodigy 60 points

    Hello Antony , 

    Just for extra information I attched a part of our qualification document  with the results of the DSP/DDR qualification.

    Best regards,

    Jeroen

    2664.QRD6001121397Rxx.pdf

  • 0 in reply to Jeroen van Andel
    TI__Mastermind 30120 points

    Hello Jeroen,

    - I am not that knowledgeable about DDR2 Jitter issues but I have seen some comments in the below document from Micron:
    http://www.micron.com/products/support/technical-notes
    Dealing with DDR2/DDR3 Clock Jitter - TN0456
    Looking at page 5 it seems that the key requirements to meet are tJITper and tJITdty. The other like tERRnper does not seem to be key. But again I am not a specialist on this.
    Have you had a look at this document already?

    - Generally speaking if the PCB layout guidelines provided in the datasheet are followed then the interface would just nicely worked. So it s key to follow those PCB layout specification.

    Hope it helps.

    AnBer