We have had some issues with the CVDD SmartReflex voltage levels, and it seems that bumping up the voltage level is beneficial. The following is what we have observed and tested:-
Problem:
- After correct power sequencing and coming out of reset, we had a problem where frequently some DSP registers could not be accessed through the JTAG debugger. When the JTAG worked, we had many DDR3 bit error problems.
- We use a TPS54320 to drive the CVDD, and a LM10011 as a D/A of the 6-bit VCNTL signals to the TPS54320 feedback. See attached schematic.
- I looked at the various power rails and the noise was minimal.
- I then investigated the VCNTL lines from the DSP that set the core voltage. This is a 6-bit digital code that is translated into voltage steps between 0.7V and 1.1V.
- After reset, the DSP delivers a “42” which translates to a desired 0.969V, and the delivered voltage was spot on.
- I first removed this VCNTL feature so that the core was a continuous 1.1V (LM10011 Rset=267K) and there was an immediate improvement. However TI warns that long term reliability can occur if the part stays in reset when 1.10V is normally delivered.
- I then re-enabled the VCNTL circuit, and changed the range to be 0.81V to 1.10V, and “42” delivered an expected 1.009V.
- JTAG loaded every time and memory tests to the DDR3 memory ran overnight.
- Attached spreadsheet shows calculations and effect of resistor changes on what DSP wants and what it gets.
- Subsequently modified to the .88V/1.1V range with Rset=200K ohm, and applied this to three boards.
- So the first/original board is doing great. The 2nd board still had issues, but when the LM10011 was removed from the circuit (R951 removed) and CVDD = 1.05V it always behaves when coming up, and gets an infrequent DDR3 bit error. The 3rdboard still has occasional JTAG start-up hiccups &/or DDR3 bit errors but it is better than it was.
Questions:-
- While we are in the prototype phase with potentially multiple issues, is it OK to run the voltage higher than requested by the DSP?
- Is it OK to go below “63”/1.1V at startup while the DSP is in reset?
- Does the TMS320C6657 operate as a Class-0 SmartReflex (one-time fixed) or as a Class-3 SmartReflex (updated based on various dynamic factors)?
- Is it possible that the factory set SmartReflex voltages are too “tight” (targeting the lowest voltage for heavily filtered power)?
- What else should we be investigating with regard to this issue?
1300.LM10010_TPS54320_Calc2.xlsx
7142.930-1081-01_Superset_Sch_1_39V5_sht47.pdf