DDR3 total access time for an AM3359 (AM335x)

Rouzbeh Karim

Other Parts Discussed in Thread: AM3359

Hello everybody!

I have a question about DDR3 total access time, I hope, that you know the answer. Also,

How many machine-cycles take approximately load/store tasks (of an ARM processor of TI-AM3359 ICE) to access a DDR3 memory, if the DDR3 is driven with the 303MHz clock and the latencies, the machine cycles of load/store instructions and cash cycles are considered in the computation?

(Assume, that the ARM Cortex-A8 is driven with 600MHz).

Best Regards

Rouzbeh

over 12 years ago

0 Biser Gatchev-XID over 12 years ago

TI__Guru**** 393215 points

Here is some input from other users who have tested memory bandwidth: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/208343.aspx

0 Rouzbeh Karim over 12 years ago in reply to Biser Gatchev-XID

Prodigy 30 points

Thank you very much for your guidance.

I think in this case, if we suppose, that the AM3359 is driven with 600MHz, and if DDR3 by 300MHz, and if DDR3 transfers two data-words per clock-cycle, then in each ARM time-period one word can be transferred. In this case, the time period is:

[t=(1/600MHz)s]

or approximately, we can say it costs ~1,67 nanosecond per data word, or ~0.834ns/Byte (I hope my computation is correct!?). (-:

But the questions are:

How long takes the ARM Load/Store Instructions? Should these add to our calculation?

Are there any cash or DMA in between? Do they need time?

Are there any other delay or latencies, which affect this value?

Best Regards

Rouzbeh

0 Biser Gatchev-XID over 12 years ago in reply to Rouzbeh Karim

TI__Guru**** 393215 points

Yes, there are internal latencies. However I don't have access to this sort of information, as it isn't publicly available. You could ask your TI Representative/FAE if it's possible to get this data.

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DDR3 total access time for an AM3359 (AM335x)